regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
7220 group users manual
7220 group. after reading this manual, the user should have a through knowledge of the functions and features of 7220 group, and should be able to fully utilize the product. the manual starts with specifications and ends with application examples. for details of software, refer to the series 740 users manual. for details of development support tools, refer to the development support tools for microcomputers data book.
7220 group, unless other wise noted. 1. organization l chapter 1 hardware this chapter describes features of the microcomputer, pin configuration, pin description, functional block diagram. l chapter 2 functional description this chapter describes operation of each peripheral function. l chapter 3 electric characteristics this chapter describes electric characteristics and standard characteristics. l chapter 4 m37220 m3-xxxsp/fp this chapter describes differences between the m37220 m3-xxxsp/fp and m37221m6-xxxsp/fp. l chapter 5 application this chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. l chapter 6 appendix this chapter includes precautions for systems development using the microcomputer, a list of control registers, the mask rom confirmation forms (mask rom version) and mark specification forms which are to be submitted when ordering.
7220 group users manual i table of contents table of contents chapter 1. overview 1.1 performance overview .......................................................................................................... 1-2 1.2 pin configuration ................................................................................................................... 1-5 1.3 pin description ...................................................................................................................... 1-7 1.4 functional block diagram ................................................................................................... 1-9 chapter 2. functional description 2.1 central processing unit ....................................................................................................... 2-2 2.1.1 accumulator (a) ............................................................................................................. 2-2 2.1.2 index register x (x), index register y (y) .................................................................. 2-2 2.1.3 stack pointer (s) ............................................................................................................ 2-3 2.1.4 program counter (pc) ................................................................................................... 2-6 2.1.5 processor status register (ps) ..................................................................................... 2-6 2.2 access area ............................................................................................................................ 2-8 2.2.1 zero page (addresses 0000 16 to 00ff 16 ) .................................................................. 2-10 2.2.2 special page (addresses ff00 16 to ffff 16 ) ............................................................ 2-10 2.3 memory assignment ........................................................................................................... 2-11 2.3.1 internal ram ................................................................................................................ 2-16 2.3.2 i/o ports (addresses 00c0 16 to 00cd 16 ) ................................................................... 2-16 2.3.3 da registers (addresses 00ce 16 and 00cf 16 ) .......................................................... 2-17 2.3.4 pwm registers (addresses 00d0 16 to 00d4 16 and 00f6 16 ) ..................................... 2-17 2.3.5 pwm output control registers (addresses 00d5 16 and 00d6 16 ) ............................. 2-17 2.3.6 multi-master i 2 c-bus related registers (addresses 00d7 16 to 00db 16 ) ................. 2-17 2.3.7 serial i/o related registers (addresses 00dc 16 and 00dd 16 ) ................................. 2-17 2.3.8 crt display related registers (addresses 00e0 16 to 00ec 16 ) ................................ 2-17 2.3.9 a-d control register (addresses 00ee 16 and 00ef 16 ) .............................................. 2-18 2.3.10 timer registers (addresses 00f0 16 to 00f3 16 ) ........................................................ 2-18 2.3.11 timer mode registers (address 00f4 16 , 00f5 16 ) .................................................... 2-19 2.3.12 cpu mode register (address 00fb 16 ) ..................................................................... 2-19 2.3.13 interrupt request registers (addresses 00fc 16 and 00fd 16 ) ................................. 2-19 2.3.14 interrupt control registers (addresses 00fe 16 and 00ff 16 ) .................................. 2-19 2.3.15 2 page register (addresses 0217 16 to 021b 16 ) (only m37221m8/ma-xxxsp) .. 2-19 2.3.16 crt display ram (addresses 0600 16 to 06b7 16 ) .................................................. 2-19 2.3.17 rom (addresses a000 16 to ffff 16 ) ........................................................................ 2-19 2.3.18 crt display rom (addresses 10000 16 to 11fff 16 ) .............................................. 2-19 2.4 input/output pins ................................................................................................................ 2-20 2.4.1 programmable ports .................................................................................................... 2-20 2.4.2 dedicated pins ............................................................................................................. 2-23 2.5 interrupts .............................................................................................................................. 2-26 2.5.1 interrupt sources .......................................................................................................... 2-27 2.5.2 interrupt control ............................................................................................................ 2-29 2.6 timers .................................................................................................................................... 2-34 2.6.1 timer functions ............................................................................................................ 2-35 2.6.2 timers 3 and timer 4 when reset and when executing stp instruction .............. 2-39 i
7220 group users manual ii table of contents 2.7 serial i/o ............................................................................................................................... 2-40 2.7.1 structure of serial i/o ................................................................................................. 2-40 2.7.2 serial i/o register (address 00dd 16 ) ......................................................................... 2-42 2.7.3 clock source generating circuit ................................................................................. 2-42 2.7.4 serial input/output common transmission/reception mode ..................................... 2-42 2.7.5 serial i/o data receive method (when an internal clock is selected) .................. 2-43 2.7.6 serial i/o data transmit method (when an external clock is selected) ................ 2-44 2.7.7 note when selecting a synchronous clock ............................................................... 2-45 2.8 multi-master i 2 c-bus interface ......................................................................................... 2-47 2.8.1 construction of multi-master i 2 c-bus interface ....................................................... 2-48 2.8.2 multi-master i 2 c-bus interface-related registers ..................................................... 2-49 2.8.3 start condition, stop condition generation method ........................................... 2-58 2.9 a-d comparator ................................................................................................................... 2-61 2.10 pwm ..................................................................................................................................... 2-63 2.10.1 8-bit pwm registers (addresses 00d0 16 to 00d4 16 and 00f6 16 ) /da registers (addresses 00ce 16 and 00cf 16 ) .................................................... 2-64 2.10.2 14-bit pwm (da output) ........................................................................................... 2-65 2.10.3 8-bit pwm (pwm0 to pwm5: address 00d0 16 to 00d4 16 and 00f6 16 ) ............. 2-67 2.10.4 14-bit pwm output control ........................................................................................ 2-69 2.10.5 8-bit pwm output control .......................................................................................... 2-70 2.11 crt display function ....................................................................................................... 2-71 2.11.1 display position .......................................................................................................... 2-74 2.11.2 character size ............................................................................................................ 2-77 2.11.3 memory for display .................................................................................................... 2-78 2.11.4 color registers ............................................................................................................ 2-82 2.11.5 multiline display ......................................................................................................... 2-84 2.11.6 character border function ......................................................................................... 2-85 2.11.7 crt output pin control ............................................................................................. 2-86 2.11.8 raster coloring function ............................................................................................ 2-87 2.11.9 clock for display ........................................................................................................ 2-88 2.12 rom correction function ................................................................................................. 2-89 2.13 software runaway detect function ................................................................................ 2-90 2.14 low-power dissipation mode ......................................................................................... 2-91 2.14.1 stop mode .................................................................................................................. 2-91 2.14.2 wait mode .................................................................................................................. 2-93 2.14.3 interrupts in low-power dissipation mode ............................................................... 2-93 2.15 reset .................................................................................................................................... 2-95 2.15.1 reset operation .......................................................................................................... 2-95 2.15.2 internal state immediately after reset ..................................................................... 2-96 2.15.3 notes for poweron reset ........................................................................................... 2-99 2.16 clock generating circuit ................................................................................................ 2-100 2.17 oscillation circuit ............................................................................................................ 2-101 chapter 3. electrical characteristics 3.1 electrical characteristics ..................................................................................................... 3-2 3.2 standard characteristics ...................................................................................................... 3-6
7220 group users manual iii table of contents chapter 4. m37220 m3-xxxsp/fp 4.1 performance overview .......................................................................................................... 4-2 4.2 pin configuration ................................................................................................................... 4-4 4.3 pin description ...................................................................................................................... 4-6 4.4 functional block diagram ................................................................................................... 4-8 4.5 functional description ......................................................................................................... 4-9 4.5.1 access area .................................................................................................................. 4-10 4.5.2 memory assignment ..................................................................................................... 4-11 4.5.3 input/output pins ......................................................................................................... 4-14 4.5.4 interrupts ....................................................................................................................... 4-15 4.5.5 d-a converter ............................................................................................................... 4-17 4.5.6 crt display function .................................................................................................. 4-19 4.5.7 internal state immediately after reset ....................................................................... 4-26 4.6 electrical characteristics ................................................................................................... 4-28 4.7 standard characteristics .................................................................................................... 4-32 chapter 5. application 5.1 example of multi-line display ............................................................................................. 5-2 5.1.1 specifications ................................................................................................................. 5-2 5.1.2 connection example ...................................................................................................... 5-2 5.1.3 general flowchart ........................................................................................................... 5-3 5.1.4 set of display character data ....................................................................................... 5-6 5.1.5 line counter .................................................................................................................... 5-7 5.1.6 processing time ............................................................................................................. 5-8 5.1.7 set of multiple interrupts .............................................................................................. 5-9 5.2 notes on programming for osd (m37220 m3-xxxsp/fp) ........................................... 5-13 5.2.1 setting of color registers ............................................................................................ 5-13 5.2.2 setting of border selection register ........................................................................... 5-14 5.2.3 number of display characters .................................................................................... 5-14 5.3 usage example of rom correction function (m37221m8/ma-xxxsp) ..................... 5-15 5.3.1 connection example .................................................................................................... 5-15 5.3.2 correction example ...................................................................................................... 5-15 5.3.3 e 2 prom map ............................................................................................................... 5-17 5.3.4 general flowchart ......................................................................................................... 5-19 5.3.5 notes on use ................................................................................................................ 5-20 5.4 example of i 2 c-bus interface control (m37221mx-xxxsp/fp) .................................. 5-21 5.4.1 specifications ............................................................................................................... 5-21 5.4.2 connection example .................................................................................................... 5-21 5.4.3 e 2 prom functions ....................................................................................................... 5-22 5.4.4 general flowchart ......................................................................................................... 5-23 5.5 example of i 2 c-bus control by software (m37220 m3-xxxsp/fp) ............................ 5-26 5.5.1 specifications ............................................................................................................... 5-26 5.5.2 connection example .................................................................................................... 5-26 5.5.3 single-chip color tv signal processor function ....................................................... 5-27 5.5.4 general flowchart ......................................................................................................... 5-28 5.5.5 data setting according to key processing ................................................................ 5-34 5.5.6 flowchart of data setting according to key processing .......................................... 5-36 5.5.7 register map ................................................................................................................ 5-39 5.6 application circuit example .............................................................................................. 5-45 5.6.1 application circuit example 1 ..................................................................................... 5-45 5.6.2 application circuit example 2 ..................................................................................... 5-46
7220 group users manual iv chapter 6. appendix 6.1 package outline ..................................................................................................................... 6-2 6.2 termination of unused pins ............................................................................................... 6-3 6.3 notes on use ......................................................................................................................... 6-4 6.3.1 notes on processor status register ............................................................................. 6-4 6.3.2 notes on decimal operation ......................................................................................... 6-5 6.3.3 notes on interrupts ........................................................................................................ 6-5 6.3.4 notes on serial i/o ........................................................................................................ 6-6 6.3.5 notes on timer ............................................................................................................... 6-7 6.3.6 notes on a-d comparator ............................................................................................. 6-8 6.3.7 note on reset pin ....................................................................................................... 6-8 6.3.8 notes on input and output pins ................................................................................... 6-9 6.3.9 note on jmp instruction ............................................................................................... 6-9 6.3.10 note on multi-master i 2 c-bus interface ................................................................. 6-10 6.3.11 termination of unused pins ...................................................................................... 6-10 6.4 counter measures against noise .................................................................................... 6-11 6.4.1 shortest wiring length ................................................................................................. 6-11 6.4.2 connection of a bypass capacitor across v ss line and v cc line ............................ 6-13 6.4.3 wiring to analog input pins ........................................................................................ 6-13 6.4.4 oscillator concerns ...................................................................................................... 6-14 6.4.5 setup for i/o ports ...................................................................................................... 6-15 6.4.6 providing of watchdog timer function by software .................................................. 6-16 6.5 memory assignment ........................................................................................................... 6-17 6.6 sfr assignment .................................................................................................................. 6-20 6.7 control registers ................................................................................................................. 6-30 6.8 ports ...................................................................................................................................... 6-51 6.9 machine instruction table .................................................................................................. 6-53 6.10 instruction code table ...................................................................................................... 6-63 6.11 mask rom ordering method ........................................................................................... 6-64 6.12 mark specification form ................................................................................................... 6-80
7220 group users manual v list of figures list of figures chapter 1. overview fig. 1.2.1 pin configuration (top view) (1) ................................................................................. 1-5 fig. 1.2.2 pin configuration (top view) (2) ................................................................................. 1-6 fig. 1.4.1 functional block diagram ............................................................................................ 1-9 chapter 2. functional description fig. 2.1.1 registers configuration diagram ................................................................................ 2-2 fig. 2.1.2 cpu mode register ...................................................................................................... 2-3 fig. 2.1.3 sequence of push onto/pop from a stack during interrupts and subroutine calls ............................................................................................................ 2-5 fig. 2.1.4 contents of stack after execution of brk instruction ............................................. 2-7 fig. 2.2.1 access area of m37221m4-xxxsp and m37221m6-xxxsp/fp ........................... 2-8 fig. 2.2.2 access area of m37221m8-xxxsp and m37221ma-xxxsp ................................. 2-9 fig. 2.3.1 memory assignment of m37221m4-xxxsp and m37221m6-xxxsp/fp ............ 2-11 fig. 2.3.2 memory assignment of m37221m8-xxxsp and m37221ma-xxxsp .................. 2-12 fig. 2.3.3 memory map of sfr (special function register) (1) ............................................. 2-13 fig. 2.3.4 memory map of sfr (special function register) (2) ............................................. 2-14 fig. 2.3.5 memory map of 2 page register (only m37221m8-xxxsp and m37221ma-xxxsp) ................................................................................................... 2-15 fig. 2.3.6 i/o setting example of port ...................................................................................... 2-16 fig. 2.3.7 access to timer registers .......................................................................................... 2-18 fig. 2.4.1 i/o pin block diagram (1) ......................................................................................... 2-24 fig. 2.4.2 i/o pin block diagram (2) ......................................................................................... 2-25 fig. 2.5.1 v sync interrupt generation timing .............................................................................. 2-27 fig. 2.5.2 interrupt control logic ................................................................................................ 2-29 fig. 2.5.3 interrupt request register 1 (address 00fc 16 ) ........................................................ 2-30 fig. 2.5.4 interrupt request register 2 (address 00fd 16 ) ........................................................ 2-30 fig. 2.5.5 interrupt control register 1 (address 00fe 16 ) ......................................................... 2-31 fig. 2.5.6 interrupt control register 2 (address 00ff 16 ).......................................................... 2-31 fig. 2.5.7 interrupt input polatiry register (address 00f9 16 ) ................................................... 2-32 fig. 2.5.8 crt port control register (address 00ec 16 ) ........................................................... 2-32 fig. 2.5.9 interrupt control system ............................................................................................ 2-33 fig. 2.5.10 interrupt vector table ............................................................................................... 2-33 fig. 2.6.1 timer 1, timer 2, timer 3, and timer 4 block diagram .......................................... 2-34 fig. 2.6.2 timer overflow timing ................................................................................................ 2-35 fig. 2.6.3 timer 12 mode register (address 00f4 16 ) .............................................................. 2-36 fig. 2.6.4 timer 34 mode register (address 00f5 16 ) .............................................................. 2-37 fig. 2.6.5 example of timer system .......................................................................................... 2-38 fig. 2.7.1 serial i/o block diagram ........................................................................................... 2-41 fig. 2.7.2 serial i/o mode register (address 00dc 16 ) ............................................................ 2-41 fig. 2.7.3 serial input/output common transfer mode block diagram ................................... 2-42 fig. 2.7.4 serial i/o register when receiving (when sm5 = 0) ........................................... 2-43 fig. 2.7.5 serial i/o register when transmitting (when sm5 = 0) ...................................... 2-44 fig. 2.7.6 timing diagram of serial i/o .................................................................................... 2-45 fig. 2.7.7 connection example for serial i/o transmit/receive .............................................. 2-46 fig. 2.7.8 serial data transmit/receive processing sequence ................................................ 2-46
7220 group users manual fig. 2.8.1 block diagram of multi-masteer i 2 c-bus interface ................................................ 2-48 fig. 2.8.2 i 2 c data shift register ................................................................................................ 2-49 fig. 2.8.3 i 2 c address register ................................................................................................... 2-50 fig. 2.8.4 i 2 c clock control register .......................................................................................... 2-52 fig. 2.8.5 connection port control by bsel0 and bsel1 ..................................................... 2-53 fig. 2.8.6 i 2 c control register ..................................................................................................... 2-54 fig. 2.8.7 interrupt request signal generating timing .............................................................. 2-57 fig. 2.8.8 i 2 c status register ...................................................................................................... 2-57 fig. 2.8.9 start condition generation timing diagram ........................................................ 2-58 fig. 2.8.10 stop condition generation timing diagram ........................................................ 2-58 fig. 2.8.11 start condition/stop condition detect timing diagram ................................... 2-59 fig. 2.8.12 address data communication format ................................................................... 2-60 fig. 2.9.1 a-d comparator block diagram ................................................................................ 2-61 fig. 2.9.2 a-d control register 1 (address 00ee 16 ) ................................................................. 2-62 fig. 2.9.3 a-d control register 2 (address 00ef 16 ) ................................................................. 2-62 fig. 2.10.1 14-bit pwm (da) block diagram ............................................................................ 2-63 fig. 2.10.2 8-bit pwm block diagram ....................................................................................... 2-64 fig. 2.10.3 14-bit pwm output example (f(x in ) = 8 mhz) ...................................................... 2-66 fig. 2.10.4 pulse waveforms corresponding to weight of each bit of 8-bit pwm register 2-68 fig. 2.10.5 example of 8-bit pwm output ................................................................................ 2-68 fig. 2.10.6 pwm output control register 1 (address 00d5 16 ) ................................................ 2-69 fig. 2.10.7 pwm output control register 2 (address 00d6 16 ) ................................................ 2-70 fig. 2.11.1 structure of crt display character ....................................................................... 2-71 fig. 2.11.2 crt display circuit block diagram ......................................................................... 2-72 fig. 2.11.3 crt control register (address 00ea 16 ) ................................................................. 2-73 fig. 2.11.4 count method of synchronous signal .................................................................... 2-74 fig. 2.11.5 display position ........................................................................................................ 2-75 fig. 2.11.6 vertical position register n (addresses 00e1 16 and 00e2 16 ) ............................... 2-76 fig. 2.11.7 horizontal position register (address 00e0 16 ) ....................................................... 2-76 fig. 2.11.8 character size register (address 00e4 16 ) ............................................................. 2-77 fig. 2.11.9 display start position (horizontal direction) for each character size ................. 2-77 fig. 2.11.10 example of display character data storing form ................................................ 2-78 fig. 2.11.11 structure of crt display ram ............................................................................ 2-81 fig. 2.11.12 color register n (addresses 00e6 16 to 00e9 16 ) .................................................. 2-82 fig. 2.11.13 generation timing of crt interrupt request ....................................................... 2-84 fig. 2.11.14 display state of blocks and occurrence of crt interrupt request .................. 2-84 fig. 2.11.15 border example ...................................................................................................... 2-85 fig. 2.11.16 border selection register (address 00e5 16 ) ........................................................ 2-85 fig. 2.11.17 crt port control register (address 00ec 16 ) ....................................................... 2-86 fig. 2.11.18 mute signal output example ............................................................................... 2-87 fig. 2.11.19 crt clock selection register ................................................................................ 2-88 fig. 2.12.1 rom correction address registers ......................................................................... 2-89 fig. 2.12.2 rom correction enable register ............................................................................. 2-89 fig. 2.13.1 sequence at detecting software runaway detection ............................................ 2-90 fig. 2.14.1 oscillation stabilizing time at return by reset input ............................................. 2-92 fig. 2.14.2 execution sequence example at return by occurrence of int0 interrupt request ...................................................................................................................... 2-92 fig. 2.14.3 reset input time ....................................................................................................... 2-93 fig. 2.14.4 state transitions of low-power dissipation mode ................................................. 2-94
7220 group users manual vii list of figures fig. 2.15.1 timing diagram at reset .......................................................................................... 2-95 fig. 2.15.2 internal state immediately after reset (1) ............................................................. 2-96 fig. 2.15.3 internal state immediately after reset (2) ............................................................. 2-97 fig. 2.15.4 internal state immediately after reset (3) (only m37221m8/ma-xxxsp) ........ 2-98 fig. 2.15.5 voltage at poweron reset ....................................................................................... 2-99 fig. 2.15.6 example of reset circuit (1) .................................................................................... 2-99 fig. 2.15.7 example of reset circuit (2) .................................................................................... 2-99 fig. 2.16.1 clock generating circuit block diagram ............................................................... 2-100 fig. 2.17.1 clock oscillation circuit using a ceramic resonator ........................................... 2-101 fig. 2.17.2 external clock input circuit example .................................................................... 2-101 fig. 2.17.3 clock oscillation circuit for crt display ............................................................. 2-101 chapter 3. electrical characteristics fig. 3.1.1 definition diagram of timing on multi-master i 2 c-bus ............................................ 3-5 chapter 4. m37220 m3-xxxsp/fp fig. 4.2.1 pin configuration (top view) (1) ................................................................................. 4-4 fig. 4.2.2 pin configuration (top view) (2) ................................................................................. 4-5 fig. 4.4.1 functional block diagram ............................................................................................ 4-8 fig. 4.5.1 access area ................................................................................................................ 4-10 fig. 4.5.2 memory assignment ................................................................................................... 4-11 fig. 4.5.3 memory map of sfr (special function register) (1) ............................................. 4-12 fig. 4.5.4 memory map of sfr (special function register) (2) ............................................. 4-13 fig. 4.5.5 interrupt request register 1 (address 00fc 16 ) ........................................................ 4-16 fig. 4.5.6 interrupt control register 1 (address 00fe 16 ) ......................................................... 4-16 fig. 4.5.7 d-a converter block diagram .................................................................................... 4-17 fig. 4.5.8 da n conversion register (addresses 00de 16 and 00df 16 ) .................................. 4-18 fig. 4.5.9 port p3 output mode control register (address 00cd 16 ) ...................................... 4-18 fig. 4.5.10 crt display circuit block diagram ......................................................................... 4-20 fig. 4.5.11 example of display character data storing form .................................................. 4-21 fig. 4.5.12 structure of crt display ram .............................................................................. 4-23 fig. 4.5.13 border selection register (addresses 00e5 16 ) ...................................................... 4-24 fig. 4.5.14 color register n (addresses 00e6 16 to 00e9 16 ) .................................................... 4-24 fig. 4.5.15 crt control register (address 00ea 16 ) ................................................................. 4-25 fig. 4.5.16 crt port control register (address 00ec 16 ) ......................................................... 4-25 fig. 4.5.17 internal state immediately after reset (1) ............................................................. 4-26 fig. 4.5.18 internal state immediately after reset (2) ............................................................. 4-27 chapter 5. application fig. 5.1.1 connection example .................................................................................................... 5-2 fig. 5.1.2 display example ........................................................................................................... 5-2 fig. 5.1.3 flowchart of initialization processing routine ........................................................... 5-3 fig. 5.1.4 flowchart of v sync interrupt processing routine ....................................................... 5-4 fig. 5.1.5 flowchart of crt interrupt processing routine ........................................................ 5-5 fig. 5.1.6 set of display character data ..................................................................................... 5-6 fig. 5.1.7 example of setup timing for line counter and display character data .................. 5-7 fig. 5.1.8 timing of interrupt processing when not setting multiple interrupts ..................... 5-9 fig. 5.1.9 timing when all interrupt request bits are 1 at the same sampling point ..... 5-10
7220 group users manual fig. 5.1.10 flowchart of crt interrupt processing routine (when setting multiple interrupts) .......................................................................... 5-11 fig. 5.1.11 flowchart of v sync interrupt processing routine (when setting multiple interrupts) .......................................................................... 5-12 fig. 5.2.1 color register n (m37221erss) .............................................................................. 5-13 fig. 5.2.2 color register n (m37220 m3-xxxsp/fp) ................................................................ 5-14 fig. 5.2.3 border selection register (m37220 m3-xxxsp/fp) ................................................ 5-14 fig. 5.3.1 connection example .................................................................................................. 5-15 fig. 5.3.2 correction example (1) ............................................................................................. 5-15 fig. 5.3.3 correction example (2) ............................................................................................. 5-16 fig. 5.3.4 e 2 prom map when using rom correction function (1) ....................................... 5-17 fig. 5.3.5 e 2 prom map when using rom correction function (2) ....................................... 5-18 fig. 5.3.6 general flowchart when using rom correction function ...................................... 5-19 fig. 5.4.1 connection example .................................................................................................. 5-21 fig. 5.4.2 byte write timing ........................................................................................................ 5-22 fig. 5.4.3 random address read timing ................................................................................... 5-22 fig. 5.4.4 flowchart of write processing routine ..................................................................... 5-23 fig. 5.4.5 flowchart of read processing routine ...................................................................... 5-24 fig. 5.4.6 flowchart of data output processing routine .......................................................... 5-25 fig. 5.5.1 connection example .................................................................................................. 5-26 fig. 5.5.2 staus read timing ....................................................................................................... 5-27 fig. 5.5.3 byte write timing ........................................................................................................ 5-27 fig. 5.5.4 flowchart of write processing routine ..................................................................... 5-28 fig. 5.5.5 flowchart of read processing routine ...................................................................... 5-29 fig. 5.5.6 flowchart of data output processing routine .......................................................... 5-30 fig. 5.5.7 flowchart of start condition processing routine ................................................ 5-31 fig. 5.5.8 flowchart of stop condition processing routine .................................................. 5-31 fig. 5.5.9 flowchart of bus h processing routine ................................................................... 5-31 fig. 5.5.10 flowchart of data input processing routine .......................................................... 5-32 fig. 5.5.11 flowchart of return ack processing routine ........................................................ 5-33 fig. 5.5.12 flowchart of return nack processing routine ..................................................... 5-33 fig. 5.5.13 flowchart of power on processing ........................................................................ 5-36 fig. 5.5.14 flowchart of ch up/down key input processing ............................................ 5-37 fig. 5.5.15 flowchart of picture memory switching key input processing ......................... 5-38 fig. 5.5.16 status data register ................................................................................................. 5-39 fig. 5.5.17 map of write data register ...................................................................................... 5-41 fig. 5.6.1 application circuit example 1 (i 2 c-bus chassis) ................................................... 5-45 fig. 5.6.2 application circuit example 2 (non-bus chassis) ................................................. 5-46 chapter 6. appendix fig. 6.3.1 initialization of flags in ps ......................................................................................... 6-4 fig. 6.3.2 stack contents after php instruction execution ...................................................... 6-4 fig. 6.3.3 note when executing plp instruction ....................................................................... 6-4 fig. 6.3.4 note in decimal arithmetic operation ........................................................................ 6-5 fig. 6.3.5 execution of bbc or bbs instruction ....................................................................... 6-5 fig. 6.3.6 sequence for switching an external interrupt detection edge ................................ 6-6 fig. 6.3.7 initialization for serial i/o ............................................................................................ 6-6 fig. 6.3.8 relation between timer values and their values read (timer setting value = 2) .............................................................................................. 6-7 fig. 6.3.9 relation between timer values and their values read when two timers are connected in series (timers 1 and 2 are connected, timer 1 setting value = 2, timer 2 setting value = 1) ............................................................................................ 6-7
7220 group users manual ix list of figures fig. 6.4.1 wiring for reset input pin ...................................................................................... 6-11 fig. 6.4.2 wiring for clock i/o pin ............................................................................................. 6-11 fig. 6.4.3 wiring for cnv ss pin ................................................................................................. 6-12 fig. 6.4.4 wiring for v pp pin of one time prom and eprom version .............................. 6-12 fig. 6.4.5 bypass capacitor across v ss line and v cc line ...................................................... 6-13 fig. 6.4.6 analog signal line and resistor and capacitor ....................................................... 6-13 fig. 6.4.7 wiring for large current signal line .......................................................................... 6-14 fig. 6.4.8 wiring for signal line where potential levels charge frequently ........................... 6-14 fig. 6.4.9 v ss pattern on underside of an oscillator ............................................................... 6-14 fig. 6.4.10 setup for i/o ports .................................................................................................. 6-15 fig. 6.4.11 watchidog timer by software .................................................................................. 6-16 fig. 6.5.1 memory assignment of m37221m4-xxxsp and m37221m6-xxxsp/fp ............ 6-17 fig. 6.5.2 memory assignment of m37221m8-xxxsp and m37221ma-xxxsp .................. 6-18 fig. 6.5.3 memory assignment of m37220 m3-xxxsp/fp ...................................................... 6-19 fig. 6.6.1 sfr assignment (including internal state immediately after reset and access access characteristics) (1) (m37221mx-xxxsp/fp) .............................................. 6-20 fig. 6.6.2 sfr assignment (including internal state immediately after reset and access access characteristics) (2) (m37221mx-xxxsp/fp) .............................................. 6-22 fig. 6.6.3 memory map of 2 page register (including internal state immediately after reset and after reset and access characteristics) (3) (only m37221m8-xxxsp and m37221ma-xxxsp) ............................................... 6-24 fig. 6.6.4 sfr assignment (including internal state immediately after reset and access after reset and access characteristics) (4) (m37220 m3-xxxsp/fp) .................. 6-26 fig. 6.6.5 sfr assignment (including internal state immediately after reset and access after reset and access characteristics) (5) (m37220 m3-xxxsp/fp) .................. 6-28 fig. 6.7.1 port pi direction register ........................................................................................... 6-30 fig. 6.7.2 port p3 direction register .......................................................................................... 6-30 fig. 6.7.3 port p5 direction register .......................................................................................... 6-31 fig. 6.7.4 port p3 output mode control register ...................................................................... 6-31 fig. 6.7.5 pwm output control register 1 ................................................................................. 6-32 fig. 6.7.6 pwm output control register 2 ................................................................................. 6-32 fig. 6.7.7 i 2 c data shift register ................................................................................................ 6-33 fig. 6.7.8 i 2 c address register ................................................................................................... 6-33 fig. 6.7.9 i 2 c status register ...................................................................................................... 6-34 fig. 6.7.10 i 2 c control register ................................................................................................... 6-35 fig. 6.7.11 i 2 c clock contorol register ...................................................................................... 6-36 fig. 6.7.12 serial i/o mode register ......................................................................................... 6-37 fig. 6.7.13 da conversion register n (only m37220 m3-xxxsp/fp) ..................................... 6-38 fig. 6.7.14 horizontal position register ..................................................................................... 6-38 fig. 6.7.15 vertical position register n ...................................................................................... 6-39 fig. 6.7.16 character size register ............................................................................................ 6-39 fig. 6.7.17 border selection register ......................................................................................... 6-40 fig. 6.7.18 color register n ........................................................................................................ 6-41 fig. 6.7.19 crt control register ................................................................................................ 6-42 fig. 6.7.20 crt port control register ........................................................................................ 6-43 fig. 6.7.21 crt clock selection register .................................................................................. 6-44 fig. 6.7.22 crt a-d control register 1 .................................................................................... 6-45 fig. 6.7.23 a-d control register 2 ............................................................................................. 6-45 fig. 6.7.24 timer 12 mode register .......................................................................................... 6-46 fig. 6.7.25 timer 34 mode register .......................................................................................... 6-47 fig. 6.7.26 interrupt input polarity register ............................................................................... 6-47 fig. 6.7.27 cpu mode register .................................................................................................. 6-48
7220 group users manual fig. 6.7.28 interrupt request register 1 ..................................................................................... 6-48 fig. 6.7.29 interrupt request register 2 ..................................................................................... 6-49 fig. 6.7.30 interrupt control register 1 ...................................................................................... 6-49 fig. 6.7.31 interrupt control register 2 ...................................................................................... 6-50 fig. 6.7.32 rom correction enable register ............................................................................. 6-50 fig. 6.8.1 i/o pin block diagram (1) ......................................................................................... 6-51 fig. 6.8.2 i/o pin block diagram (2) ......................................................................................... 6-52
7220 group users manual xi list of tables 7220 group users manual xi list of tables chapter 1. overview table 1.1.1 performance overview (1) ........................................................................................ 1-3 table 1.1.2 performance overview (2) ........................................................................................ 1-4 table 1.3.1 pin description (1) .................................................................................................... 1-7 table 1.3.2 pin description (2) .................................................................................................... 1-8 chapter 2. functional description table 2.2.1 zero page addressing ............................................................................................ 2-10 table 2.2.2 special page addressing ........................................................................................ 2-10 table 2.4.1 list of programmable port functions .................................................................... 2-22 table 2.5.1 interrupt sources, vector addresses and priority ................................................ 2-26 table 2.6.1 memory map of timer-related registers ................................................................ 2-37 table 2.6.2 contents of timers 3 and 4 when reset or when executing stp instruction 2-39 table 2.7.1 clock source selection ........................................................................................... 2-42 table 2.8.1 multi-master i 2 c-bus interface functions ............................................................. 2-47 table 2.8.2 start condition/stop condition generation timing table ................................ 2-58 table 2.8.3 start condition/stop condition detect conditions .......................................... 2-59 table 2.9.1 relationship between contents of a-d control register 2 and reference voltage vref .......................................................................................................... 2-62 table 2.10.1 pwm function performance (at oscillation frequency = 8 mhz) ..................... 2-63 table 2.10.2 the relation between d l and t m ( m = 0 to 63) ............................................. 2-65 table 2.11.1 outline of crt display function .......................................................................... 2-71 table 2.11.2 relationship between set value in character size register and character size ......................................................................................................................... 2-77 table 2.11.3 character code table (be omitted partly) .......................................................... 2-79 table 2.11.4 contents of crt display ram ............................................................................ 2-80 table 2.11.5 display example of character background coloring (when green is set for a character and blue is set for background color) .......................................... 2-83 table 2.11.6 relationship between set value of border selection register and character border function ...................................................................................................... 2-85 table 2.14.1 state in stop mode ............................................................................................... 2-91 table 2.14.2 state in wait mode ............................................................................................... 2-93 table 2.14.3 invalid interrupts in the wait mode ..................................................................... 2-93
7220 group users manual chapter 4. m37220 m3-xxxsp/fp table 4.1.1 performance overview (1) ........................................................................................ 4-2 table 4.1.2 performance overview (2) ........................................................................................ 4-3 table 4.3.1 pin description (1) .................................................................................................... 4-6 table 4.3.2 pin description (2) .................................................................................................... 4-7 table 4.5.1 difference between m37220 m3-xxxsp/fp and m37221m6-xxxsp/fp ........... 4-9 table 4.5.2 difference of programmable ports between m37221m6-xxxsp/fp and m37220 m3-xxxsp/fp ........................................................................................... 4-14 table 4.5.3 interrupt sources, vector addresses and priority ................................................ 4-15 table 4.5.4 relationship between contents of d-a conversion register and output voltage v output voltage v ................................................................................................... 4-17 table 4.5.5 outline of crt display function ............................................................................ 4-19 table 4.5.6 character code table (be omitted partly) ............................................................. 4-22 table 4.5.7 contents of crt display ram .............................................................................. 4-22 chapter 5. application table 5.5.1 data setting at tuning and searching ................................................................... 5-34 table 5.5.2 data setting at volume up/down key input ................................................... 5-34 table 5.5.3 data setting at screen-size-related keys input ................................................. 5-34 table 5.5.4 data setting at picture data control key and picture memory switching key input .................................................................. 5-34 table 5.5.5 data setting when changing aft state ............................................................... 5-35 table 5.5.6 data setting when changing audio mute state ................................................... 5-35 table 5.5.7 data setting when changing video mute state ................................................... 5-35 table 5.5.8 data setting when adjusting white balance ......................................................... 5-35 table 5.5.9 relationship between dfa and dl time ............................................................ 5-42 table 5.5.10 setting of color system (at sub-address 09 16 , write data) .............................. 5-43 chapter 6. appendix table 6.2.1 termination of unused pins ..................................................................................... 6-3
7220 group users manual overview 1.1 performance overview 1.1 performance overview the 8-bit microcomputers: -m37221m4-xxxsp -m37221m6-xxxsp/fp -m37221m8-xxxsp -m37221ma-xxxsp -m37220 m3-xxxsp/fp have their simple instruction set; the rom, ram, and i/o addresses are placed on the same memory map to enable easy programming. furthermore, they have many additional functions for tuning system for tv: l pwm output (14-bit and 8-bit) l crt display l a-d comparator (resistance string method) l software runaway detection l multi-master i 2 c-bus interface function l rom correction function and also, they can allow low power dissipation by the use of cmos processing. the m37221m6-xxxsp/fp is used as a general example in describing the functions of the above microcomputers, unless otherwise noted.
7220 group users manual 71 0.5 s (the minimum instruction execution time, at 8 mhz oscillation frequency) 8 mhz (maximum) rom 16 k bytes ram 320 bytes rom 24 k bytes ram 384 bytes rom 32 k bytes ram 512 bytes rom 40 k bytes ram 640 bytes 8 k bytes 96 bytes 8-bit 5 1 (n-channel open-drain output structure, can be used as pwm output pins, int input pins, a-d input pin) 4-bit 5 1 (cmos input/output structure, can be used as crt output pin, a-d input pins, int input pin) 4-bit 5 1 (cmos input/output structure, can be used as multi-master i 2 c-bus interface) 2-bit 5 1 (cmos input/output or n-channel open-drain output structure, can be used as serial i/o pins) 6-bit 5 1 (cmos input/output structure, can be used as serial input pin, external clock input pins) 2-bit 5 1 (cmos input/output or n-channel open-drain output structure, can be used as a-d input pins) 1-bit 5 1 (n-channel open-drain output structure) 2-bit 5 1 (can be used as crt display clock i/o pins) 4-bit 5 1 (cmos output structure, can be used as crt output pins) 8-bit 5 1 1 (2 systems) 6 channels (6-bit resolution) 14-bit 5 1, 8-bit 5 6 8-bit timer 5 4 32 bytes 5 2 number of basic instructions instruction execution time clock frequency memory size input/output ports serial i/o multi-master i 2 c-bus interface a-d comparator pwm output circuit timers rom correction function (see note) the performance overview is shown in table 1.1.1. m37220 m3-xxxsp/fp refer to chapter 4. m37220 m3-xxxsp/fp. table 1.1.1 performance overview (1) 1.1 performance overview parameter performance i/o i/o i/o i/o i/o i/o i/o input output m37221m4-xxxsp m37221m6-xxxsp/fp m37221m8-xxxsp m37221ma-xxxsp crt rom crt ram p0 0 Cp0 7 p1 0 , p1 5 Cp1 7 p1 1 Cp1 4 p2 0 , p2 1 p2 2 Cp2 7 p3 0 , p3 1 p3 2 p3 3 , p3 4 p5 2 Cp5 5
7220 group users manual overview subroutine nesting interrupt clock generating circuit power source voltage power dissipation 12v withstand ports led drive ports operating temperature range device structure package crt display function 1.1 performance overview table 1.1.2 performance overview (2) performance parameter 96 levels (maximum) 128 levels (maximum) external interrupt 5 3, internal timer interrupt 5 4, serial i/o interrupt 5 1, crt interrupt 5 1, multi-master i 2 c- bus interface interrupt 5 1, f(x in )/4096 interrupt 5 1, v sync interrupt 5 1, brk interrupt 5 1 2 built-in circuits (externally connected to a ceramic resonator or a quartz-crystal oscillator) 5 v 10 % 165 mw typ. (at oscillation frequency f(x in ) = 8 mhz, f crt = 8 mhz) 110 mw typ. (at oscillation frequency f(x in ) = 8 mhz) 1.65 mw (maximum) 6 4 C10 c to 70 c cmos silicon gate process 42-pin shrink plastic molded dip 42-pin shrink plastic molded sop 24 characters 5 2 lines (maximum 16 lines by software) 12 5 16 dots 256 kinds 3 kinds maximum 7 kinds (r, g, b); can be specified by the character 64 levels (horizontal) 5 128 levels (vertical) m37221m4-xxxsp m37221m6-xxxsp/fp m37221m8-xxxsp m37221ma-xxxsp crt on crt off in stop mode m37221m4-xxxsp m37221m6-xxxsp m37221m8-xxxsp m37221ma-xxxsp m37221m6-xxxfp number of display characters dot structure kinds of characters kinds of character sizes kinds of character colors display position (horizontal, vertical) note: only m37221m8-xxxsp and m37221ma-xxxsp have the function.
7220 group users manual 1.2 pin configuration 1.2 pin configuration the pin configurations are shown in figures 1.2.1 and 1.2.2. m37220 m3-xxxsp/fp refer to chapter 4. m37220 m3-xxxsp/fp. fig. 1.2.1 pin configuration (top view) (1) h sync v sync p0 0 /pwm0 p0 2 /pwm2 p0 1 /pwm1 p0 3 /pwm3 p0 4 /pwm4 p0 5 /pwm5 p0 6 /int2/a-d4 p0 7 /int1 p2 3 /tim3 p2 4 /tim2 p2 5 p2 6 p3 2 p2 7 d-a cnv ss x out v ss p3 1 /a-d6 p1 0 /out2 p2 1 /s out p2 2 /s in p1 2 /scl2 p1 1 /scl1 p1 3 /sda1 p1 4 /sda2 p1 5 /a-d1/int3 p1 6 /a-d2 p1 7 /a-d3 osc1/p3 3 reset osc2/p3 4 v cc p3 0 /a-d5 x in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 outline 42p4b p5 2 /r p5 4 /b p5 3 /g p5 5 /out1 p2 0 /s clk 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 42 41 40 39 38 37 m37221m4-xxxsp m37221m6-xxxsp m37221m8-xxxsp m37221ma-xxxsp overview
7220 group users manual overview fig. 1.2.2 pin configuration (top view) (2) 1.2 pin configuration h sync v sync p0 0 /pwm0 p0 2 /pwm2 p0 1 /pwm1 p0 3 /pwm3 p0 4 /pwm4 p0 5 /pwm5 p0 6 /int2/a-d4 p0 7 /int1 p2 3 /tim3 p2 4 /tim2 p2 5 p2 6 p3 2 p2 7 d-a cnv ss x out v ss p3 1 /a-d6 p1 0 /out2 p2 1 /s out p2 2 /s in p1 2 /scl2 p1 1 /scl1 p1 3 /sda1 p1 4 /sda2 p1 5 /a-d1/int3 p1 6 /a-d2 p1 7 /a-d3 osc1/p3 3 reset osc2/p3 4 v cc p3 0 /a-d5 x in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 outline 42p2r-a p5 2 /r p5 4 /b p5 3 /g p5 5 /out1 p2 0 /s clk 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 42 41 40 39 38 37 m37221m6-xxxfp
7220 group users manual power source cnv ss reset input clock input clock output i/o port p0 pwm output external interrupt input analog input i/o port p1 crt output multi-master i 2 c-bus interface analog input external interrupt input input input output i/o output input input i/o output i/o input input apply voltage of 5 v 10 % (typical) to v cc , and 0 v to v ss . connected to v ss . to enter the reset state, the reset input pin must be kept at a l for 2 s or more (under normal v cc conditions). if more time is needed for the quartz-crystal oscillator to stabilize, this l condition should be maintained for the required time. this chip has an internal clock generating circuit. to control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins x in and x out . if an external clock is used, the clock source should be connected to the x in pin and the x out pin should be left open. port p0 is an 8-bit i/o port with direction register allowing each i/o bit to be individually programmed as input or output. at reset, this port is set to input mode. the output structure is n-channel open-drain output. pins p0 0 Cp0 5 are also used as pwm output pins pwm0Cpwm5 respectively. the output structure is n-channel open-drain output. pins p0 6 , p0 7 are also used as external interrupt input pins int2, int1 respectively. p0 6 pin is also used as analog input pin a-d4. port p1 is an 8-bit i/o port and has basically the same functions as port p0. the output structure is cmos output. pins p1 0 is also used as crt output pin out2. the output structure is cmos output. pins p1 1 Cp1 4 are used as scl1, scl2, sda1 and sda2 respectively, when multi-master i 2 c-bus interface is used. the output structure is n-channel open-drain output. pins p1 5 Cp1 7 are also used as analog input pins a-d1 to a-d3 respectively. p1 5 pin is also used as external interrupt input pin int3. v cc , v ss cnv ss ______ reset x in x out p0 0 pwm0C p0 5 / pwm5, p0 6 /int2/ a-d4 , p0 7 /int1 p1 0 /out2, p1 1 /scl1, p1 2 /scl2, p1 3 /sda1, p1 4 /sda2, p1 5 /a-d1/ int3, p1 6 /a-d2, p1 7 /a-d3 1.3 pin description 1.3 pin description the pin description is shown in table 1.3.1. m37220 m3-xxxsp/fp refer to chapter 4. m37220 m3-xxxsp/fp. table 1.3.1 pin description (1) pin name input/ output functions overview
7220 group user?s manual overview 1.3 pin description table 1.3.2 pin description (2) pin name input/ output functions port p2 is an 8-bit i/o port and has basically the same func tions as port p0. the output structure is cmos output. pins p2 3 , p2 4 are also used as external clock input pins tim3, tim2 respectively. p2 0 pin is also used as serial i/o synchronous clock input/outp ut pin s clk . the output structure is n-channel open-drain output. pins p2 1 , p2 2 are also used as serial i/o data input/output pins s out , s in respectively. the output structure is n-channel open-drain output. ports p3 0 Cp3 2 are 3-bit i/o ports and have basically the same functions as port p0. either cmos output or n-channel open-drain outpu t structure can be selected as the port p3 0 and p3 1 . the output structure of port p3 2 is n-channel open-drain output. pins p3 0 , p3 1 are also used as analog input pins a-d5, a-d6 respectively . ports p3 3 , p3 4 are 2-bit input ports. p3 3 pin is also used as crt display clock input pin osc1. p3 4 pin is also used as crt display clock output pin osc2. the output structure is cmos output. ports p5 2 Cp5 5 are 4-bit output ports. the output structure is cmos output. pins p5 2 Cp5 5 are also used as crt output pins r, g, b, out1 respectively. the output structure is cmos output. this is a horizontal synchronous signal input for crt. this is a vertical synchronous signal input for crt. this is a 14-bit pwm output pin. the output structure is cmo s output. i/o input i/o i/o i/o input input input output output output input input output i/o port p2 external clock input serial i/o synchronous clock input/ output serial i/o data input/output i/o port p3 analog input input port p3 clock input for crt display clock output for crt display output port p5 crt output h sync input v sync input da output p2 0 /s clk , p2 1 /s out , p2 2 /s in , p2 3 /tim3, p2 4 /tim2, p2 5 Cp2 7 p3 0 /a-d5/ da1, p3 1 /a-d6/ da2, p3 2 p3 3 /osc1, p3 4 /osc2 p5 2 /r, p5 3 /g, p5 4 /b, p5 5 /out1 h sync v sync d-a
7220 group users manual 1.4 functional block diagram 1.4 functional block diagram the functional block diagram is shown in figure 1.4.1. m37220 m3-xxxsp/fp refer to chapter 4. m37220 m3-xxxsp/fp. fig. 1.4.1 functional block diagram out1 clock input clock output x in x out reset input v cc v ss cnv ss clock output for display input ports p3 3, p3 4 osc1 osc2 clock input for display int2 int1 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 p5 (4) b g r h sync v sync a-d comparator 14-bit pwm circuit 8-bit pwm circuit accumulator a (8) timer 4 t4 (8) timer 3 t3 (8) timer 2 t2 (8) timer 1 t1 (8) timer count source selection circuit tim2 tim3 instruction register (8) instruction decoder control signal crt circuit stack pointer s (8) index register y (8) index register x (8) processor status register ps (8) 8-bit arithmetic and logical unit rom program counter pc l (8) program counter pc h (8) ram data bus clock generating circuit reset output ports p5 2 Cp5 5 address bus si/o(8) s in s clk s out int3 10 9 8 7 6 5 4 3 i/o port p0 28 29 30 31 32 33 34 35 p1 (8) i/o port p1 15 14 13 12 11 36 37 38 p2 (8) i/o port p2 i/o ports p3 0 Cp3 2 17 26 27 16 p3 (3) p0 (8) 39 40 41 42 2 1 20 19 25 22 21 18 24 23 d-a out2 multi-master i c-bus interface 2 rom correction function (see note) note : only m38221m8-xxxsp and m37221ma-xxxsp have the function.
7220 group users manual 2.1 central processing unit the cpu of the m37221m6-xxxsp/fp has six main registers. the program counter (pc) is a 16-bit register consists of pc h and pc l , both of which are 8-bit registers. the other five registers: the accumulator (a), index register x (x), index register y (y), stack pointer (s) and processor status register (ps), all have an 8-bit configuration. note: the contents of registers above except the following are indeterminate after a hardware reset. therefore, initialize these registers by software. ? the interrupt disable flag i of the processor status register = 1 ? the program counter = the contents of addresses fffe 16 and ffff 16 figure 2.1.1 shows the registers configuration diagram of m37221m6-xxxsp/fp. 7 0 7 0 7 0 7 0 7 0 a x y s nvtbd i z pc l decimal operation mode flag break flag x modified operation mode flag overflow flag negative flag 7 0 pc h 7 0 c accumulator (a) index register x (x) index register y (y) stack pointer (s) program counter (pc) processor status register (ps) carry flag zero flag interrupt disable flag fig. 2.1.1 registers configuration diagram 2.1.1 accumulator (a) the accumulator is the central register of the microcomputer and 8-bit register. this general-purpose register is used with considerable for arithmetic operations, data transfer, temporary clearing, condition judgments, etc. 2.1.2 index register x (x), index register y (y) the m37221m6-xxxsp/fp has the index register x and the index register y, both of which are 8-bit registers. in the addressing modes which use these index registers, the register contents are added to the specified address and this becomes the actual address. these modes are used for referencing subroutine tables and memory tables. the index registers, which have increment, decrement, comparison and data transfer functions, are also used as simple accumulators.
7220 group users manual functional description 2.1 central processing unit 2.1.3 stack pointer (s) the stack pointer is an 8-bit register used for interrupts and subroutine calls. the stack area can be assigned into the internal ram. the internal ram of m37221m6-xxxsp/fp is assigned in the zero page and the page 1. the both area can use for the stack area. the stack area is specified with the cpu mode register (address 00fb 16 ). at reset, the stack area is specified to the page 1 automatically. note: storing data in the stack area fills the ram area with stored data in order, therefore make sure the depth of interrupt levels and the subroutine nesting. the stack area and stack pointer (s) should be specified in the initialization of software. when the stack area is specified to 1, even if the value of stack pointer is over 00 16 (stack address is 0100 16 ), the stack area value never change to 0 automatically. therefore in this case, change the stack area value by software. b7 b6 b5 b4 b3 b2 b1 b0 cpu mode register (cpum) (cm) [address 00fb 16 ] b after reset rw cpu mode register 0, 1 2 3 to 5 0 1 name functions fix these bits to 0. fix these bits to 1. 1 stack page selection bit (cm2) 1 0: 0 page 1: 1 page 10 0 6, 7 indeterminate note: this bit is set to 1 after reset release. 1 11 rw rw rw rw fig. 2.1.2 cpu mode register with the stack pointer during a interrupt or subroutine call, the processing is performed automatically in the following sequence (refer to figure 2.1.3 ). the contents of high-order 8 bits of the program counter (pc h ) are stored at an address indicated as below: ? the high-order 8 bits are the stack area value (00 16 or 01 16 ). ? the low-order 8 bits are the stack pointer contents. the stack pointer contents are decremented by 1. a the contents of low-order 8 bits of the program counter (pc l ) are stored at an address indicated as below: ? the high-order 8 bits are the stack area value (00 16 or 01 16 ). ? the low-order 8 bits are the stack pointer contents. ? the stack pointer contents are decremented by 1. ? the contents of the processor status register (ps) are stored at an address indicated as below: ? the high-order 8 bits are the stack area value (00 16 or 01 16 ). ? the low-order 8 bits are the stack pointer contents. ? the stack pointer contents are decremented by 1. (note)
7220 group users manual storing of the processor status register in items ? and ? above is not performed during a subroutine call. execute the php instruction in a program to push the processor status register onto a stack. to prevent data from losing during interrupts and subroutine calls, push the other registers onto a stack by software as described above. for example, execute the pha instruction to push the accumulator contents onto a stack. executing the pha instruction stores the accumulator contents at an address indicated as below: ? the high-order 8 bits are the stack area value (00 16 or 01 16 ). ? the low-order 8 bits are the stack pointer contents. the stack pointer contents are then decremented by 1. execute the rti instruction to return from an interrupt routine. when the rti instruction is executed, the processing is performed automatically in the following sequence (refer to figure 2.1.3 ). the stack pointer contents are incremented by 1. the contents at the address indicated as below are restored to the processor status register. ? the high-order 8 bits are the stack area value (00 16 or 01 16 ). ? the low-order 8 bits are the stack pointer contents. a the stack pointer contents are incremented by 1. ? the contents at the address indicated as below are restored to low-order 8 bits of the program counter (pc l ). ? the high-order 8 bits are the stack area value (00 16 or 01 16 ). ? the low-order 8 bits are the stack pointer contents. ? the stack pointer contents are incremented by 1. ? the contents at the address indicated as below are restored to high-order 8 bits of the program counter (pc h ). ? the high-order 8 bits are the stack area value (00 16 or 01 16 ). ? the low-order 8 bits are the stack pointer contents. restoring of the processor status register in items and above is not performed in this case. execute the rts instruction to return from a subroutine. execute the plp instruction and pla instruction to restore the processor status register and the accumulator, respectively. executing the plp ( pla ) instruction increments the stack pointer by 1 and restores the contents at the address indicated as below to the processor status register. ? the high-order 8 bits are the stack area value (00 16 or 01 16 ). ? the low-order 8 bits are the stack pointer.
7220 group users manual functional description 2.1 central processing unit ? ? ? ? ? ? ? ? on-going routine (pc h ) m(s) (s)C1 (s) (pc l ) m(s) (s)C1 (s)C1 (ps) m(s) (s) (s) (pc h ) m(s) (s)+1 (s) (pc l ) m(s) (s)+1 (s)+1 (ps) m(s) (s) (s) execute rt i interrupt routine execute jsr (pc h ) m(s) (s)C1 (s) (pc l ) m(s) (s)C1 (s) (pc h ) m(s) (pc l ) m(s) (s)+1 (s)+1 (s) (s) execute rts ? ? ? subroutine ? ? ? ? ? ? ? ? interrupt request ? ? ? (pc h ) : contents of high-order 8 bits of program counter : contents of low-order 8 bits of program counter : contents of processor status register : contents of stack pointer : memory : instruction for returning from interrupt routine to main routine : instruction for returning from subroutine to main routine m rti rts (pc l ) (ps) (s) fig. 2.1.3 sequence of push onto/pop from a stack during interrupts and subroutine calls
7220 group users manual 2.1.4 program counter (pc) the program counter is a 16-bit counter consists of pc h and pc l , both of which are 8-bit registers. the program counter indicates the address of the program to be executed next. the m37221m6-xxxsp/fp uses the stored program system. to start a new operation, transfer the instruction and the data, from the memory to the cpu. ordinary, the program counter is controlled to indicate the memory address to be sent next. after each instruction is executed, the instruction required next is called out and this cycle is repeated until finished. note: the program counter of the m37221m6-xxxsp/fp is controlled automatically; however, make sure to avoid differences between program flow and the program counter contents when operating the stack pointer or directly changing the program counter contents. 2.1.5 processor status register (ps) the processor status register is an 8-bit register. it consists of 5 flags, which indicate the state after arithmetic operations related to the internal cpu, and 3 flags which determine operation. the following explains each of these flags. refer to 6.9 machine instruction table of this users manual or series 740 users manual concerning the change of these flags. (1) carry flag (c) ...................................................... bit 0 this flag stores any carry or borrow from the alu after an arithmetic operation and is also changed by the shift instruction or rotate instruction. this flag is set to 1 by using the sec instruction and is cleared to 0 by using the clc instruction. (2) zero flag (z) ........................................................ bit 1 this flag is set to 1 when the result of an arithmetic operation or a data transfer is 0 and is cleared to 0 by any other result. this flag has no meaning in the decimal mode. (3) interrupt disable flag (i) ................................... bit 2 this flag disables interrupts. when this flag is 1, all interrupts except the brk interrupt and reset are disabled. this flag immediately becomes 1 when an interrupt is received. this flag is set to 1 by using the sei instruction and is cleared to 0 by using the cli instruction. (4) decimal operation mode flag (d) ................... bit 3 this flag determines whether addition and substruction are performed in binary or decimal notation. binary arithmetic is performed when this flag is 0 and decimal arithmetic is performed with treating each word as a 2-digit decimal when this flag is 1. decimal adjust is performed automatically at this time. this flag is set to 1 by using the sed instruction and is cleared to 0 by using the cld instruction. only the adc and sbc instructions are used for decimal arithmetic. since this flag directly affects calculations, always initialize it after a reset. (5) break flag (b) ...................................................... bit 4 this flag determines whether or not an interrupt occurred by using the brk instruction. when a brk instruction interrupt occurs, the flag b is set to 1; for all other interrupts the flag is set to 0 and pushed to the stack. for the m37221m6-xxxsp/fp, interrupt vectors by using the brk instruction are independent of other interrupts, and it is possible to determine the cause of interrupt by jumping to the vector address inherent to each interrupt. therefore, it is not specifically necessary to refer to this flag. note: the brk instruction will be used for debugging.
7220 group users manual functional description 2.1 central processing unit 74 0 1 =b flag ps (processor status register) pc h (high-order of program counter) pc l (low-order of program counter) bit s s+1 s+2 s+3 fig. 2.1.4 contents of stack after execution of brk instruction (6) x modified operation mode flag (t) .............. bit 5 this flag determines whether arithmetic operations are performed via the accumulator or directly between memories. when the flag is set to 0, arithmetic operations are performed between the accumulator and memory. when 1, arithmetic operations are performed directly between memories. this flag is set to 1 with the set instruction and is cleared to 0 with the clt instruction. since this flag directly affects calculations, always initialize it after a reset. n when the t flag = 0 a ? a ] m ] : indicates an arithmetic operation a : accumulator contents m: contents of the memory specified by the addressing of the arithmetic operation n when the t flag = 1 m1 ? m1 ] m2 ] : indicates arithmetic operation m1: contents of memory specified directly with index register x m2: contents of the memory specified by the addressing of the arithmetic operation (7) overflow flag v ................................................... bit 6 this flag is set to 1 when an overflow occurs in the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction exceeds +127 (7f 16 ) or C128 (80 16 ). the clv instruction clears the overflow flag to 0. there is no instruction for setting this flag to 1. when the bit instruction is executed except the above, bit 6 of the memory executed by the bit instruction is set to the overflow flag. this flag has no meaning in decimal mode. note: overflows do not occur when the result of an addition or subtraction is smaller than the above numerical values or an addition is performed between different signs. (8) negative flag (n) ......................................................... bit 7 this flag is set to 1 when the result of a data transfer or arithmetic operation is negative (bit 7 is 1). when the bit instruction is executed, bit 7 of the memory executed by the bit instruction is set to the negative flag. this flag can be used to determine whether the results of arithmetic operations are positive or negative, and also to perform a simple bit test. there are no instructions for directly setting or clearing this flag. this flag has no meaning in decimal mode.
7220 group users manual 2.2 access area the rom, ram and various i/o control registers are assigned within the same memory area. therefore, the same instructions are used for data transfers and arithmetic operations without making any distinction between memory and i/o. since the program counter is a 16-bit register, 64 k-byte memory area can be accessed: from addresses as 0000 16 to ffff 16 . the first 256 bytes of the 64 k-byte memory area are called the zero page and the last 256 bytes are called the special page. these areas can be accessed with only 2 bytes by using each special addressing mode. m37220 m3-xxxsp/fp refer to chapter 4. m37220 m3-xxxsp/fp. 0000 16 00c0 16 00ff 16 017f 16 06b7 16 a000 16 sfr area special function register (refer to figures 2. 3. 3 and 2. 3. 4) not used not used ffff 16 ffde 16 ff00 16 0600 16 interrupt vector area not used 10000 16 11fff 16 1ffff 16 zero page crt display rom (8 k bytes) special page rom (16 k bytes) for m37221m4 crt display ram (96 bytes) (see note) note: refer to table 2.11.4 contents of crt display ram. internal ram ram for display internal rom internal ram rom for display : internal rom area for program counter 01bf 16 ram (320 bytes) for m37221m4 c000 16 rom (24 k bytes) for m37221m6 ram (384 bytes) for m37221m6 fig. 2.2.1 access area of m37221m4-xxxsp and m37221m6-xxxsp/fp
7220 group users manual 2.2 access area functional description sfr area special function register (refer to figures 2. 3. 3 to 2. 3. 5) internal ram rom for display : internal rom area for program counter 0000 16 00c0 16 00ff 16 01ff 16 rom correction memory (ram) ffff 16 ffde 16 ff00 16 interrupt vector area not used 10000 16 11fff 16 1ffff 16 special page rom (32 k bytes) for m37221m8 zero page 033f 16 0300 16 02ff 16 02c0 16 0217 16 not used 2 page register not used 021b 16 note: refer to table 2.11.4 contents of crt display ram. internal ram internal rom internal ram rom correction memory block 1: addresses 02c0 16 to 02df 16 block 2: addresses 02e0 16 to 02ff 16 crt display rom (8 k bytes) 06b7 16 6000 16 not used 0600 16 not used ram for display crt display ram (96 bytes) (see note) 03bf 16 ram (512 bytes) for m37221m8 8000 16 rom (40 k bytes) for m37221ma ram (640 bytes) for m37221ma fig. 2.2.2 access area of m37221m8-xxxsp and m37221ma-xxxsp
7220 group users manual 2.2.1 zero page (addresses 0000 16 to 00ff 16 ) the 256 bytes from address 0000 16 to address 00ff 16 are called zero page. the internal ram, i/o ports, timer, serial i/o, a-d comparison, pwm output, crt display and interrupt related registers all present within this area. these registers were called special function registers in distinction from the accumulator, index registers and so on in the cpu. the addressing modes as shown in table 2.2.1 are used to specify memory (ram) and special function registers in the zero page area. those modes dedicated to the zero page area are marked with a symbol ( ] ). this area can be accessed with shorter instructions by using these modes. table 2.2.1 zero page addressing 2 2 2 2 2 3 3 3 3 2 3 2 2 ] zero page ] zero page indirect ] zero page x ] zero page y ] zero page bit ] zero page bit relative absolute absolute x absolute y relative indirect indirect x indirect y bytes required addressing mode 2.2.2 special page (addresses ff00 16 to ffff 16 ) the 256 bytes from address ff00 16 to address ffff 16 within the internal rom are called special page area. the addressing modes as shown in table 2.2.2 are used to specify memory in the special page area. those modes dedicated to the special page area are marked with a symbol ( ] ). this area can be accessed with shorter instructions by using these modes. subroutines used with considerable frequency are ordinary assigned in this area. bytes required 2 3 3 3 2 3 2 2 table 2.2.2 special page addressing addressing mode ] special page absolute absolute x absolute y relative indirect indirect x indirect y
7220 group users manual 2.3 memory assignment functional description 2.3 memory assignment figures 2.3.1 and 2.3.2 show the memory assignment. the rom, ram and i/o assigned in this memory area are described below. m37220 m3-xxxsp/fp refer to chapter 4. m37220 m3-xxxsp/fp. sfr area special function register (refer to figures 2. 3. 3 and 2. 3. 4) not used not used interrupt vector area zero page special page internal ram ram for display internal rom internal ram decimal notation 0 255 383 1719 40960 65535 65502 65280 1536 192 49152 0000 16 00c0 16 00ff 16 017f 16 06b7 16 a000 16 ffff 16 ff00 16 0600 16 rom (16 k bytes) for m37221m4 crt display ram (96 bytes) (see note) 01bf 16 ram (320 bytes) for m37221m4 c000 16 rom (24 k bytes) for m37221m6 ram (384 bytes) for m37221m6 447 not used 10000 16 11fff 16 1ffff 16 note: refer to table 2.11.4 contents of crt display ram. rom for display 65536 73727 131071 crt display rom (8 k bytes) hexadecimal notation 0100 16 fig. 2.3.1 memory assignment of m37221m4-xxxsp and m37221m6-xxxsp/fp
7220 group users manual fig. 2.3.2 memory assignment of m37221m8-xxxsp and m37221ma-xxxsp sfr area special function register (refer to figures 2. 3. 3 to 2. 3. 5) internal ram rom for display rom correction memory (ram) interrupt vector area not used 10000 16 11fff 16 1ffff 16 crt display rom (8 k bytes) not used 2 page register not used note: refer to table 2.11.4 contents of crt display ram. internal ram internal rom internal ram zero page special page hexadecimal notation decimal notation 65535 65502 65280 0 192 255 511 not used not used ram for display 1719 24576 1536 959 767 704 535 540 65536 73727 rom correction memory block 1: addresses 02c0 16 to 02df 16 block 2: addresses 02e0 16 to 02ff 16 768 131071 0000 16 00c0 16 00ff 16 01ff 16 ffff 16 ffde 16 ff00 16 rom (32 k bytes) for m37221m8 033f 16 0300 16 02ff 16 02c0 16 0217 16 021b 16 06b7 16 6000 16 0600 16 crt display ram (96 bytes) (see note) 03bf 16 ram (512 bytes) for m37221m8 8000 16 rom (40 k bytes) for m37221ma ram (640 bytes) for m37221ma 831 32768 0100 16
7220 group users manual 2.3 memory assignment functional description p30s p31s pw0 pw1 pw2 pw3 pw4 pw5 pw6 pw7 pn2 pn3 pn4 sm0 sm1 sm2 sm3 sm5 sm6 b7 b0 ? 00 16 b7 b0 ? 00 16 ? 00 16 ? ? ? ? ? 0 0 0 ? ? 0 0 ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? ? ? ? ? 00 16 ? 0 ? ? ? sad0 sad1 sad2 sad3 sad4 sad5 sad6 rbw lrb ad0 aas al pin bb trx mst bc0 bc1 bc2 es0 als 10 bit sad bsel0 bsel1 ccr0 ccr1 ccr2 ccr3 ccr4 fast mode ack bit ack 00 16 00 16 00 16 0 0 00 0 1? 0 n sfr area (addresses c0 16 to df 16 ) d0 16 d1 16 d2 16 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 c0 16 c1 16 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c9 16 cb 16 cc 16 cd 16 ce 16 cf 16 ca 16 address port p5 (p5) port p5 direction register (d5) port p3 output mode control register (p3s) da-h register (da-h) da-l register (da-l) pwm0 register (pwm0) port p1 (p1) port p1 direction register (d1) port p3 (p3) port p3 direction register (d3) port p2 (p2) port p2 direction register (d2) register port p0 (p0) port p0 direction register (d0) pwm1 register (pwm1) pwm2 register (pwm2) pwm3 register (pwm3) pwm4 register (pwm4) pwm output control register 1 (pw) pwm output control register 2 (pn) serial i/o mode register (sm) serial i/o register (sio) bit allocation state immediately after reset i c data shift register (s0) 2 i c address register (s0d) 2 i c status register (s1) 2 i c control register (s1d) 2 i c clock control register (s2) 2 00 16 00 16 : indeterminate immediately after reset : 0 immediately after reset 0 1 ? < state immediately after reset > : 1 immediately after reset : fix this bit to 0 (do not write 1) : < bit allocation > function bit : no function bit : fix this bit to 1 (do not write 0) name : 1 0 d1 d2 d3 d4 d5 d6 d7 d0 0 0 00 16 00 16 00 16 00 16 00 16 00 16 00 16 fig. 2.3.3 memory map of sfr (special function register) (1)
7220 group users manual fig. 2.3.4 memory map of sfr (special function register) (2) b7 b0 hr0 hr1 hr2 hr3 hr4 hr5 cv10 cv11 cv12 cv13 cv14 cv15 cv16 cv20 cv21 cv22 cv23 cv24 cv25 cv26 cs10 cs11 cs20 cs21 md10 md20 co01 co02 co03 co05 co11 co12 co13 co15 co21 co22 co23 co25 co31 co32 co33 co35 cc0 cc1 cc2 vsyc r/g/b out1 op5 op6 op7 hsyc ck0 ck1 adm0 adm1 adm2 adm4 adc0 adc1 adc2 adc4 adc3 adc5 t34m0 t34m1 t34m2 t34m3 t34m4 t12m0 t12m1 t12m2 t12m3 t12m4 ck0 re5 re4 re3 cm2 tm1r tm2r tm3r tm4r crtr vscr it3r ck0 msr 1t1r 1t2r s1r tm1e tm2e tm3e tm4e crte vsce it3e 1t1e 1t2e s1e mse t34m5 co04 co14 co24 co34 co06 co16 co26 co36 co07 co17 co27 co37 cc7 out2 iicr iice f0 16 f1 16 f2 16 f3 16 f4 16 f5 16 f6 16 f7 16 f8 16 f9 16 fa 16 fb 16 fc 16 fd 16 fe 16 ff 16 e0 16 e1 16 e2 16 e3 16 e4 16 e5 16 e6 16 e7 16 e8 16 e9 16 eb 16 ec 16 ed 16 ee 16 ef 16 ea 16 address crt control register (cc) crt port control register (crtp) a-d control register 1 (ad1) a-d control register 2 (ad2) timer 1 (tm1) vertical position register 2 (cv2) color register 0 (co0) color register 1 (co1) character size register (cs) border selection register (md) register horizontal position register (hr) vertical position register 1 (cv1) timer 2 (tm2) timer 3 (tm3) timer 4 (tm4) timer 12 mode register (t12m) timer 34 mode register (t34m) pwm5 register (pwm5) interrupt input polarity register (re) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) color register 2 (co2) color register 3 (co3) crt clock selection register (ck) cpu mode register (cpum) bit allocation n sfr area (addresses e0 16 to ff 16 ) : fix this bit to 0 (do not write 1) : < bit allocation > function bit : no function bit : fix this bit to 1 (do not write 0) name : 1 0 00 00 0 0 0 0 00 16 11111 00 00 0 00 00 ? b7 b0 0 ?????? ? 0 ?????? ? ???? 0000 ?? 00000 0 ? 00 16 ? 00 000 0 0 ff 16 07 16 ff 16 07 16 ? ? ? 00 00 0? 0 1 ? 0 00 16 ? 11 1 00 state immediately after reset 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 : 0 immediately after reset 0 1 ? < state immediately after reset > : 1 immediately after reset : indeterminate immediately after reset
7220 group users manual 2.3 memory assignment functional description fig. 2.3.5 memory map of 2 page register (only m37221m8-xxxsp and m37221ma-xxxsp) 217 16 218 16 219 16 21a 16 21b 16 b7 b0 rcr1 b7 b0 ? ? rcr0 ? ? address register rom correction address 1 (high-order) bit allocation state immediately after reset n 2 page register area (addresses 217 16 to 21b 16 ) rom correction address 1 (low-order) rom correction address 2 (high-order) rom correction address 2 (low-order) rom correction enable register (rcr) : fix this bit to 0 (do not write 1) : < bit allocation > function bit : no function bit : fix this bit to 1 (do not write 0) name : 1 0 adl20 00 adl21 adl22 adl23 adl24 adl25 adl26 adl27 adh20 adh21 adh22 adh23 adh24 adh25 adh26 adh27 adl10 adl11 adl12 adl13 adl14 adl15 adl16 adl17 adh10 adh11 adh12 adh13 adh14 adh15 adh16 adh17 : 0 immediately after reset 0 1 ? < state immediately after reset > : 1 immediately after reset : indeterminate immediately after reset 00 16 note: only m37221m8-xxxsp and m37221ma-xxxsp have this area.
7220 group users manual 2.3.1 internal ram the static ram is assigned. the internal ram is used as a stack area for subroutine calls and interrupts as well as for storing data. both zero page and page 1 are used as a stack area. at reset, the page 1 is specified automatically. ordinary, the stack pointer is set to the highest address in the internal ram of the page 1 during initialization immediately after power on. this stack pointer moves to lower addresses as the nesting depth increases; therefore, make sure the subroutine nesting and interrupt levels to prevent the stored data destroying necessary data in the ram. when the stack page is specified 1, if the value of stack pointer exceeds address 0100 16 , the value of stack page never change to 0 automatically. in this case, set the stack page value to 0 and set the stack pointer value to the highest address by software. 2.3.2 i/o ports (addresses 00c0 16 to 00cd 16 ) addresses 00c0 16 to 00cd 16 are assigned to the ports, port direction registers and the port p3 output mode control register. there are 5 ports: p0, p1, p2, p3 and p5. ports p0, p1 and p2 are the 8-bit programmable i/o ports. port p3 consists of 5 bits. the low-order 3 bits (p3 0 Cp3 2 ) are the programmable i/o ports, and the high-order 2 bits (p3 3 and p3 4 ) are the input ports. for i/o ports p0, p1, p2 and p3 0 Cp3 2 , input or output can be specified in bit units by setting the relevant values to each port direction register. to specify port bits as output pins, write 1 to the corresponding bit of the port direction register. conversely, write 0 to the corresponding bit to specify as an input pin. for example, to use the even numbered bits of port p2 as output ports and the odd numbered bits as input ports, write 55 16 (01010101 2 ) to address 00c5 16 (the port p2 direction register) at initialization. although port p5 is an output port, it can be specified as the crt output pins (r, g, b, out1) or as general-purpose port (p5 2 Cp5 5 ) by setting each bit in the port p5 direction register. when setting 0, it is used for the crt output pins (r, g, b, out1), and when setting 1, it is used as general-purpose output ports (p5 2 Cp5 5 ). note: each port direction register default is input (port p5 is crt output) immediately after reset release. fig. 2.3.6 i/o setting example of port 0 1 2 3 4 5 6 7 00c4 16 00c5 16 port p2 direction register bit port p2 bit port p2 port p2 direction register write 55 16 to port p2 direction register 01010101 input output 76543210 input output output output input input
7220 group user?s manual 2.3 memory assignment functional description 2.3.3 da registers (addresses 00ce 16 and 00cf 16 ) the da-h register is assigned to address 00ce 16 , and the da-l register is assigned to address 00cf 16 . both registers consist of 8 bits. the da-h register is used to set the high-order 8 bits of 14 -bit pwm output data. the da-l register is used to set the low-order 6 bits of 14-bit pwm output data (set t o bits 0 to 5). bits 7 is not used. 2.3.4 pwm registers (addresses 00d0 16 to 00d4 16 and 00f6 16 ) the pwm0 to pwm4 registers are assigned to addresses 00d0 16 to 00d4 16 and pwm5 register is address 00f6 16 . all registers consist of 8 bits. these registers are used to set the output data correspondin g to six 8-bit pwm (pwm0Cpwm5). 2.3.5 pwm output control registers (addresses 00d5 16 and 00d6 16 ) the pwm output control register 1 is assigned to address 00d 5 16 and the pwm output control register 2 is assigned to address 00d6 16 . both registers consist of 8 bits, and used to select the pwm count source etc. the high-order 3 bits and the low-order 2 bits of the pwm output control register 2 ar e not used. 2.3.6 multi-master i 2 c-bus related registers (addresses 00d7 16 to 00db 16 ) the i 2 c data shift register, the i 2 c address register, the i 2 c status register, i 2 c control register and the i 2 c clock control register are assigned to addresses 00d7 16 , 00d8 16 , 00d9 16 , 00da 16 and 00db 16 respectively. all registers consist of 8 bits. the i 2 c data shift register is a 8-bit shift register to store rec eive data and write transmit data. the i 2 c address register consists of a 7-bit slave address and a r ead/write bit. the i 2 c status register controls the i 2 c-bus interface status. the low-order 4 bits are read-only b its and the high-order 4 bits can be read out and written to. the i 2 c control register controls data communication format. the i 2 c clock control register is used to set ack control, scl mod e and scl frequency. 2.3.7 serial i/o related registers (addresses 00dc 16 and 00dd 16 ) the serial i/o mode register is assigned to address 00dc 16 and the serial i/o register is assigned to address 00dd 16 . both registers consist of 8 bits. the serial i/o mode register is used to select the synchrono us clock and the serial i/o port function by its low-order 4 bits. bit 5 selects the transfer direction, and bit 6 selects the serial data input pin. bit 4 is set to 0. bit 7 is not used. the serial i/o register is used to write transfer data. 2.3.8 crt display related registers (addresses 00e0 16 to 00ec 16 ) (1) horizontal position register (address 00e0 16 ) the horizontal position register is assigned to address 00e0 16 . this register consists of 8 bits, and is used to specify the horizontal position of crt display. b its 7 and 6 are not used. (2) vertical display position registers (addresses 00e1 16 and 00e2 16 ) the vertical display position register 1 is assigned to addr ess 00e1 16 and the vertical display position register 2 is assigned to address 00e2 16 . these registers are corresponded to blocks 1 and 2, and used to set the vertical position to start display. bit 7 of each register is not used. (3) character size register (address 00e4 16 ) the character size register is assigned to address 00e4 16 . this register consists of 8 bits, and is used to specify one of the three sizes of display characters. bit s 4 to 7 are not used.
7220 group users manual (4) border selection register (address 00e5 16 ) the border selection register is assigned to address 00e5 16 . this register consists of 8 bits, and is used to set the border for blocks 1 and 2 by using one bit each. bits 1 and 3 to 7 are not used. (5) color registers (addresses 00e6 16 to 00e9 16 ) color registers 0 to 3 are assigned to addresses 00e6 16 to 00e9 16 . all color registers consist of 8 bits, and are used to set character output, blank output and character background color by crt output (r, g, b, out1). bit 0 is not used. (6) crt control register (address 00ea 16 ) the crt control register is assigned to address 00ea 16 . this register consists of 8 bits, and is used to set display on/off for each block. bits 3 to 6 are not used. (7) crt port control register (address 00ec 16 ) the crt port control register is assigned to address 00ec 16 . this register consists of 8 bits, and is used to set the input polarity (h sync and v sync ) and the output polarity (r, g, b, out1 and out2). 2.3.9 a-d control registers (addresses 00ee 16 and 00ef 16 ) the a-d control register 1 is assigned to address 00ee 16 , the a-d control register 2 is assigned to address 00ef 16 . both registers consist of 8 bits the a-d control register 1 is used to select analog input pins and hold the results of comparator operation. bits 3 and 5 to 7 are not used. the a-d control register 2 is used to set the internal analog voltage. bits 6 and 7 are not used. 2.3.10 timer registers (addresses 00f0 16 to 00f3 16 ) the timer registers are assigned to addresses 00f0 16 to 00f3 16 . both the timer and timer latch are written in this area when writing, but only the timer is read when reading. to write data to address 00f1 16 , for example, the data are stored to the timer 2 latch and timer 2. after that, the timer 2 contents are decremented by synchronizing with the clock pulse but the timer 2 latch contents are not changed. accordingly, when reading data at address 00f1 16 , the contents of timer 2 is read out at the time. fig. 2.3.7 access to timer registers at read access data loading at timer 2 overflow timer 2 latch timer 2 counting (down count) reading the contents of timer 2 data setting timer 2 timer 1 timer 3 timer 4 addresses 00f0 16 00f1 16 00f2 16 00f3 16
7220 group user?s manual 2.3 memory assignment functional description 2.3.11 timer mode registers (address 00f4 16 and 00f5 16 ) the timer 12 mode register is assigned to address 00f4 16 and the timer 34 mode register is assigned to address 00f5 16 . both registers consist of 8 bits. they select the count so urce of timer and control the count stop bit. bits 5 to 7 of the timer 12 mode register and bits 6, 7 of the timer 34 mode register are not used. 2.3.12 cpu mode register (address 00fb 16 ) the cpu mode register is assigned to address 00fb 16 . this register consists of 8 bits, and specifies the stack page. set bits 0 and 1 are set to 0, and set bits 3 to 7 to 0. 2.3.13 interrupt request registers (addresses 00fc 16 and 00fd 16 ) the interrupt request register 1 is assigned to address 00fc 16 and the interrupt request register 2 is assigned to address 00fd 16 . both registers consist of 8 bits, and hold content of each interrupt request bit. bits 3 and 5 to 7 of the interrupt request register 2 are no t used. 2.3.14 interrupt control registers (addresses 00fe 16 and 00ff 16 ) the interrupt control register 1 is assigned to address 00fe 16 and the interrupt control register 2 is assigned to address 00ff 16 . both registers consist of 8 bits, and sets enable/disable of interrupts. bits 7 to 5 and 3 of the interrupt control register 2 are no t used. 2.3.15 2 page register (addresses 0217 16 to 021b 16 ) (only m37221m8-xxxsp and m37221ma-xxxsp) (1) rom correction addresses (address 0217 16 to 021a 16 ) addresses 0217 16 to 021a 16 are assigned to rom correction address. the rom data addres ses to be corrected are set to the rom correction addresses. (2) rom correction enable register (address 021b 16 ) the rom correction enable register is assigned to address 02 1b 16 . this register consist of 8 bits, and controls the rom correction function. bits 2 to 7 are no t used. 2.3.16 crt display ram (addresses 0600 16 to 06b7 16 ) the display ram is used to specify the character to be displ ayed on the crt and its color. two addresses are used for one character: one address (8 bits) to specify each character code and the other (8 bits) to specify the color of the character. 2.3.17 rom (addresses a000 16 to ffff 16 ) the mask rom is assigned. in this internal rom, addresses ffde 16 , ffdf 16 , ffe4 16 , fff5 16 , and fff8 16 to ffff 16 are assigned to vector area for reset and for interrupts. a vector jump dest ination storage address (16 bits) are stored in 2 addresses by the 1 interrupt source. 2.3.18 crt display rom (addresses 10000 16 to 11fff 16 ) the display rom stores (masks) character patterns of each ch aracter to be displayed on the crt. although one character consists of 16 (vertical) 12 (horizontal) dots, it is divided into a 16 8 dot and a 16 4 dot pattern, with each pattern stored in one address. in oth er words, two addresses (16 bits) are used for one character. the rom can store up to 256 kinds of characte rs.
7220 group users manual 2-20 2.4 input/output pins the m37221m6-xxxsp/fp has 33 programable ports (i/o ports, input ports, output ports). the double- function ports function as ports and as pins for internal peripheral devices. m37220 m3-xxxsp/fp refer to chapter 4. m37220 m3-xxxsp/fp. l double-function ports .................... p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 4 , p3 0 , p3 1 p5 2 Cp5 5 l i/o port-only ports ......................... p2 5 Cp2 7 , p3 2 and also, the m37221m6-xxxsp/fp has 9 pins with only the dedicated function. l dediated pins ................................. ________ v cc , v ss , reset, x in , cnv ss , x out , d-a, h sync , v sync 2.4.1 programmable ports (1) port p0 port p0 is an 8-bit input/output port. this is an n-channel open drain output. port p0 is assigned to memory at address 00c0 16 on zero page. port p0 has the direction register (at address 00c1 16 on zero page), so that it is possible to program each bit whether the port is used for input or output. the pins of which the direction register is programmed to 0 are set for input; when programmed to 1, the pins are set for output. when pins are programmed as output pins, the output data are written into the port latch and then output. when reading data from the output pins, the output pin level is not read but the port latch data is read. this allows a previously-output value to be read correctly even if the output low voltage has risen, for example, because a light emitting diode was directly driven. the input pins float, so the values of the pins can be read. when writing data into the input pin, it is written only into the port latch, while the pin remains floating. ports p0 0 Cp0 5 are also used as pwm output pins pwm0Cpwm5 respectively. port p0 6 is also used as external interrupt pin int2 and analog input pin a-d4. the p0 7 pin is also used as external interrupt input pin int1. when external interrupts int1 and int2 are enabled, an interrupt is processed according to transition in the level on these pins. ports p0 6 and p0 7 have the schmit characteristics when they are used as int input pins. in this case, set these pins for input by the port p0 direction register.
7220 group users manual (2) port p1 port p1 is an 8-bit i/o port. the output structure is cmos output, however, only when ports p1 1 C p1 4 are used as multi-master i 2 c-bus interface, the output structure is n-channel open-drain output. port p1 has basically the same function as port p0. port p1 0 is also used as crt output pin out2. pin out2 is a crt output pin. when setting 1 to bit 7 of the crt control register, the pin functions as crt output pin, when setting 0, the pin functions as a general-purpose i/o port. ports p1 1 Cp1 4 are used as scl1, scl2, sda1 and sda2 respectively. port p1 5 is also used as external interrupt input pin int3 and analog input pin a-d1. ports p1 6 and p1 7 are also used as analog input pins a-d2 and a-d3 respectively. (3) port p2 port p2 is an 8-bit i/o port. the output structure is cmos output, however, only when ports p2 0 and p2 1 are used as serial i/o pins, the output structure is n-channel open-drain output. port p2 has basically the same function as port p0. port p2 0 is also used as serial i/o synchronous clock input/output pin s clk . port p2 1 is also used as serial i/o data output pin s out . port p2 2 is also used as serial i/o data input pin s in . port p2 3 is also used as external clock input pin tim3. when the timer 3 count source is supplied form an external device (as set by the timer 34 mode register), the input signal to this pin is the timer 3 count source. the port p2 4 is also used as external clock input pin tim2. when the count source for timer 2 is supplied form an external device (as set by the timer 12 mode register), the input signal to this pin is the timer 2 count source. ports p2 5 Cp2 7 has only i/o port function. (4) port p3 ports p3 0 Cp3 2 are 3-bit i/o ports, ports p3 3 and p3 4 are a 2-bit input port. for the output structure of ports p3 0 and p3 1 , either cmos output or n-channel open-drain output structure can be selected by bit 0 or 1 of the port p3 output mode control register (address 00cd 16 ). when 1, n-channel open- drain output structure is selected; when 0, cmos output structure is selected. port p3 2 has only i/o port function. the output structure is n-channel open-drain output. port p3 2 has basically the same function as port p0. ports p3 0 and p3 1 are also used as analog input pins a-d5 and a-d6 respectively. ports p3 3 and p3 4 are also used as crt display clock input pins osc1 and osc2 respectively. pin osc1 is a clock input for crt display, pin osc2 is a clock output for crt display. the output structure of pin osc2 is cmos output. (5) port p5 ports p5 2 Cp5 5 are 4-bit output ports. the output structure is cmos output. ports p5 2 Cp5 5 are also used as crt output pins r, g, b, out1 respectively. pins r, g, b, and out1 are crt output pins. when setting each bit of the port p5 direction register to 0, the pins function as crt output pins; when setting to 1, the pins function as general-purpose output ports. the output structure of crt output pin is cmos output structure.
7220 group users manual 2-22 p0 0 Cp0 5 p0 6 p0 7 p1 0 p1 1 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p2 0 p2 1 p2 2 p2 3 p2 4 p2 5 Cp2 7 p3 0 p3 1 p3 2 p3 3 p3 4 p5 2 p5 3 p5 4 p5 5 table 2.4.1 list of programmable port functions ports name functions except port pwm0Cpwm5 int2/a-d4 int1 out2 scl1 scl2 sda1 sda2 a-d1/int3 a-d2 a-d3 s clk s out s in tim3 tim2 a-d5 a-d6 osc1 osc2 r g b out1 pwm output pin external interrupt input pin/analog input pin external interrupt input pin crt output pin multi-master i 2 c-bus interface pin multi-master i 2 c-bus interface pin multi-master i 2 c-bus interface pin multi-master i 2 c-bus interface pin analog input pin/external interrupt pin analog input pin analog input pin serial i/o synchronous clock input/output pin serial i/o data input /output pin serial i/o data input pin external clock input pin external clock input pin function as only programmable i/o ports analog input pin analog input pin functions as only programmable i/o port. crt display clock input pin crt display clock output pin crt output pin crt output pin crt output pin crt output pin
7220 group users manual 2.4.2 dedicated pins (1) 14-bit pwm output (d-a) pin this is a 14-bit pwm signal output pin. this pin also can be used for 1-bit general-purpose output port. the output structure is cmos output. (2) vertical and horizontal synchronous signal input pins (v sync , h sync ) these pins input the vertical and horizontal synchronous signals for crt display. (3) test input pin (cnv ss ) connect this pin to v ss . (4) reset input pin (reset) this pin inputs reset signal. to reset the microcomputer, hold the reset pin at a low level for 2 s or more. reset is released when high level is applied to the reset pin. for details, refer to 2.15 reset. (5) clock i/o pins (x in , x out ) these pins are i/o pins of main clock f(x in ). since a microcomputer has on-chip clock oscillation circuit, set the oscillation frequency by connecting an external ceramic resonator or a quartz-crystal oscillator between pins x in and x out . when inputting an external clock, connect the external clock to the x in pin and leave the x out pin open. the output structure of x out pin is cmos output. (6) power source input pin (v cc , v ss ) these pins supply the power source to a microcomputer. apply voltage of 5 v 10 % to pin v cc and 0 v to pin v ss .
7220 group users manual 2-24 p0 6 /int2/a-d4, p0 7 /int1 n-channel open-drain output data bus direction register port latch n-channel open-drain output p0 0 /pwm0Cp0 5 /pwm5, p3 2 data bus direction register port latch p1 0 /out2, p1 1 /scl1, p1 2 /scl2, p1 3 /sda1, p1 4 /sda2, p1 5 /a-d1/int3, p1 6 /a-d2, p1 7 /a-d3, p2 0 /s clk , p2 1 /s out , p2 2 /s in , p2 3 /tim3, p2 4 /tim2, p2 5 Cp2 7 , p3 0 /a-d5, p3 1 /a-d6 cmos output notes 1 : data bus direction register port latch when ports p1 1 Cp1 4 are used as multi-master i c-bus interface pin and when ports p2 serial i/o output pins, their output structure is n-channel open-drain output. for the output structure of ports p3 (in the case of n-channel open-drain output, the block diagram is the same as below). 2 : 2 indicates a pin. 0 , p2 1 are used as 0 , p3 1 , either cmos output or n-channel open-drain output is selected fig. 2.4.1 i/o pin block diagram (1)
7220 group users manual cmos output d-a, p5 2 /r, p5 3 /g, p5 4 /b, p5 5 /out1 input p3 3 /osc1, p3 4 internal circuit internal circuit schmidt input h sync , v sync h sync or v sync indicates a pin. fig. 2.4.2 i/o pin block diagram (2)
7220 group users manual functional description 2.5 interrupts 2.5 interrupts interrupts are used in the following cases. l when there is a request to execute a higher priority routine than current processing routine. l when it is necessary to process according to a certain timing. the m37221m6-xxxsp/fp has 14 interrupt sources (including reset). these are vector interrupts with a fixed priority sequence. table 2.5.1 shows the interrupt sources, vector addresses and the interrupt priority sequence. m37220 m3-xxxsp/fp refer to chapter 4. m37220 m3-xxxsp/fp. note: reset are included in the table because it operates in the same way as interrupts. these 14-source, 14-vector interrupts have the priority sequence as shown in table 2.5.1 (reset has a higher priority than interrupts). when two or more interrupt requests occur at the same sampling point, the interrupt with the higher priority (in order of 1 to 14) is received. this priority sequence is determined by hardware, but priority processing is possible to be varied by software, by using the interrupt enable bit and the interrupt disable flag. table 2.5.1 interrupt sources, vector addresses and priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 reset (note) crt interrupt int2 interrupt int1 interrupt timer 4 interrupt f(x in )/4096 interrupt v sync interrupt timer 3 interrupt timer 2 interrupt timer 1 interrupt serial i/o interrupt multi-master i 2 c-bus interface interrupt int3 interrupt brk instruction interrupt high-order byte ffff 16 fffd 16 fffb 16 fff9 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffdf 16 low-order byte fffe 16 fffc 16 fffa 16 fff8 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffde 16 vector addresses non-maskable active edge selectable active edge selectable active edge selectable active edge selectable non-maskable (software interrupt) priority interrupt sources remarks
7220 group users manual functional description 2.5 interrupts 2.5.1 interrupt sources the following explains interrupt sources, in order of priority (except reset). (1) crt interrupt when displaying a character block with the crt display function, the crt interrupt request occurs at the completion of the display. (2) int2 interrupt an int2 interrupt request is generated by detecting a level transition on pin int2 (external interrupt input). detecting either positive polarity (low to high transition) or negative polarity (high to low transition) is set with re4 (the interrupt input polarity register: bit 4 at address 00f9 16 ). when re4 is set to 0, a positive polarity is detected; when re4 is set to 1, a negative polarity is detected. the int2 pin is also used for port p0 6 and pin a-d4. an int2 interrupt by a level transition on the pin may cause software runaway. therefore, when this pin is used as port p0 6 , disable an int2 interrupt by using an interrupt enable bit and the interrupt disable flag (i). (3) int1 interrupt an int1 interrupt request is generated by detecting a level transition on pin int1 (external interrupt input). detecting either positive polarity (low to high transition) or negative polarity (high to low transition) to be detected is set with re3 (the interrupt input polarity register: bit 3 at address 00f9 16 ). when re3 is set to 0, a positive polarity is detected; when re3 is set to 1, a negative polarity is detected. pin int1 is also used for port p0 7 . an int1 interrupt by a level transition on the pin may cause software runaway. therefore, when this pin is used as port p0 7 , disable the int1 interrupt by using an interrupt enable bit and interrupt disable flag (i). (4) timer 4 interrupt timer 4 value is counted down. timer 4 interrupt request occurs when the count source next to 00 16 is input. (5) f(x in )/4096 interrupt a f(x in )/4096 interrupt request occurs for a f(x in )/4096 period. this interrupt is valid when the pwm count source is supplied (when bit 0 of pwm output control register 1 is 0). (6) v sync interrupt a v sync interrupt request occurs synchronized with the vertical synchronous signal which is input to pin v sync . when the v sync input polarity is positive (the crt port control register: bit 1 at address 00ec 16 is 0), an interrupt request is generated by a rising edge (low to high transition) of the v sync input; conversely, when the polarity is negative, an interrupt request is generated by a falling edge. v sync input pin : interrupt request is generated positive polarity input negative polarity input fig. 2.5.1 v sync interrupt generation timing
7220 group users manual functional description 2.5 interrupts (7) timer 3 interrupt timer 3 value is counted down. timer 3 interrupt request occurs when the count source next to 00 16 is input. (8) timer 2 interrupt timer 2 value is counted down. timer 2 interrupt request occurs when a count source next to 00 16 is input (9) timer 1 interrupt timer 1 value is counted down. timer 1 interrupt request occurs when a count source next to 00 16 is input. (10) serial i/o interrupt the serial i/o interrupt request is generated by detecting a rising edge of the eighth serial transfer clock after writing to the serial i/o register. (11) multi-master i 2 c-bus interface interrupt a multi-master interrupt request occurs synchronized with a falling edge serial clock (scl) every completion of 1-byte data communication. (12) int3 interrupt an int3 interrupt request is generated by detecting a transition in the level on pin int3 (external interrupt input). detecting either positive polarity (low to high transition) or negative polarity (high to low transition) to be detected is set with re5 (the interrupt input polarity register: bit 5 at address 00f9 16 ). when re5 is set to 0, a positive polarity is detected, when re5 is set to 1, a negative polarity is detected. pin int3 is also used for port p1 5 and pin a-d1. an int3 interrupt by a level transition on the pin may cause software runaway. therefore, when this pin is used as port p1 5 , disable an int3 interrupt by using an interrupt enable bit and interrupt disable flag (1). (13) brk instruction interrupt this software interrupt has the least significant priority and generates an interrupt request is generated by executing when the brk instruction. there is no corresponding interrupt enable bit and no influence by the interrupt disable flag (i).
7220 group users manual functional description 2.5 interrupts 2.5.2 interrupt control each interrupt can be controlled with the interrupt request bit, the interrupt control bit, and the interrupt disable flag. reset interrupt enable bit interrupt disable flag (i) start of interrupt process interrupt request bit brk instruction fig. 2.5.2 interrupt control logic (1) interrupt request bit when an interrupt request occurs, the corresponding bit of the interrupt request register is set to 1. the interrupt request is held active until an interrupt is accepted or 0 is written to the relevant bit by software. the bit is automatically cleared to 0 simultaneously when the interrupt is accepted. interrupt request bits are cleared to 0 (to clear the interrupt request) by software but are not set to 1 (to generate the interrupt request) by software. each interrupt request bit is assigned to interrupt request registers 1 and 2 (addresses 00fc 16 and 00fd 16 ). (2) interrupt enable bit interrupt enable bits control the acceptance of each interrupt. when the interrupt enable bit is cleared to 0 (to disable an interrupt), the interrupt cannot be accepted. conversely, when the interrupt enable bit is set to 1 (to enable an interrupt), the interrupt is accepted. however, if the interrupt disable flag is set to 1, the interrupt cannot be accepted even when the interrupt enable bit is set to 1. each interrupt enable bit is assigned to interrupt control registers 1 and 2 (addresses 00fe 16 and 00ff 16 ). (3) interrupt disable flag (i) the interrupt disable flag (i) is assigned to bit 2 of the processor status register. when the interrupt disable flag is set to 1, all interrupts except the brk instruction interrupt are disabled; when the flag is cleared to 0, interrupts are enabled. however, if the interrupt disable flag is cleared to 0, the interrupt cannot be accepted even when the interrupt enable bit is 0.
7220 group users manual functional description 2.5 interrupts fig. 2.5.4 interrupt request register 2 (address 00fd 16 ) b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 1 (ireq1) [address 00fc b name functions after reset rw interrupt request register 1 0 0 : no interrupt request issued 1 : interrupt request issued timer 1 interrupt request bit (tm1r) 1 timer 2 interrupt request bit (tm2r) 2 timer 3 interrupt request bit (tm3r) 3 timer 4 interrupt request bit (tm4r) 4 crt interrupt request bit (crtr) 5v sync interrupt request bit (vscr) 6 multi-master i 2 c-bus interface interrupt request bit (iicr) 7 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] ] : 0 can be set by software, but 1 cannot be set. int3 interrupt request bit (it3r) 0 : no interrupt request issued 1 : interrupt request issued ] 16 ] r r r r r r r r b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 2 (ireq2) [address 00fd b name functions after reset rw interrupt request register 2 0 int1 interrupt request bit (itir) 0 : no interrupt request issued 1 : interrupt request issued 1 int2 interrupt request bit (it2r) 2 serial i/o interrupt request bit (s1r) 3 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. 4 f(x in )/4096 interrupt request bit (msr) 5, 6 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 7 fix this bit to 0. 0 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 ] : 0 can be set by software, but 1 cannot be set. 0 0 ] 0 0 ] 0 ] 0 ] 0 : no interrupt request issued 1 : interrupt request issued 16 ] r r r r r r rw fig. 2.5.3 interrupt request register 1 (address 00fc 16 )
7220 group users manual functional description 2.5 interrupts b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 1 (icon1) [address 00fe 16 ] b name functions after reset rw interrupt control register 1 0 timer 1 interrupt enable bit (tm1e) 0 : interrupt disabled 1 : interrupt enabled 0 1 timer 2 interrupt enable bit (tm2e) 0 2 timer 3 interrupt enable bit (tm3e) 0 3 timer 4 interrupt enable bit (tm4e) 0 4 crt interrupt enable bit (crte) 0 5 v sync interrupt enable bit (vsce) 0 6 multi-master i 2 c-bus interface interrupt enable bit (iice) 0 0 7 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled int3 interrupt enable bit (it3e) 0 : interrupt disabled 1 : interrupt enabled rw rw rw rw rw rw rw rw fig. 2.5.6 interrupt control register 2 (address 00ff 16 ) b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 2 (icon2) [address 00ff 16 ] b name functions after reset rw interrupt control register 2 0 int1 interrupt enable bit (it1e) 0 : interrupt disabled 1 : interrupt enabled 1 int2 interrupt enable bit (it2e) 2 serial i/o interrupt enable bit (s1e) 3 fix this bit to 0. 4 f(x in )/4096 interrupt enable bit (mse) 5 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled fix these bits to 0. 0 0 0 0 0 0 00 0 0 to 7 rw rw rw rw rw rw fig. 2.5.5 interrupt control register 1 (address 00fe 16 )
7220 group users manual functional description 2.5 interrupts fig. 2.5.7 interrupt input polatiry register (address 00f9 16 ) fig. 2.5.8 crt port control register (address 00ec 16 ) b7 b6 b5 b4 b3 b2 b1 b0 crt port control register(crtp) [address 00ec 16 ] b name functions after reset r w crt port control register 0h sync input polarity switch bit (hsyc) 0 : positive polarity 1 : negative polarity 0 1 0 : positive polarity 1 : negative polarity 0 2 r, g, b output polarity switch bit (r, g, b) 0 : positive polarity 1 : negative polarity 0 3 out2 output polarity switch bit (out2) 0 : positive polarity 1 : negative polarity 0 4 out1 output polarity switch bit (out1) 0 : positive polarity 1 : negative polarity 0 5 r signal output switch bit (op5) 0 : r signal output 1 : mute signal output 0 6 g signal output switch bit (op6) 0 : g signal output 1 : mute signal output 0 7 b signal output switch bit (op7) 0 : b signal output 1 : mute signal output 0 v sync input polarity switch bit (vsyc) rw rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 interrupt input polarity register(re) [address 00f9 16 ] b name functions after reset r w interrupt input polarity register 0 int1 polarity switch bit (re3) 1, 2 0 0 3 0 : positive polarity 1 : negative polarity 0 4 0 : positive polarity 1 : negative polarity 0 5 0 : positive polarity 1 : negative polarity 0 6 0 7 0 0 0 int2 polarity switch bit (re4) int3 polarity switch bit (re5) nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. fix these bits to 0. fix this bit to 0. nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. indeterminate r rw rw rw rw r rw
7220 group users manual functional description 2.5 interrupts fff0 16 fff1 16 fff2 16 fff3 16 fff4 16 fff5 16 fff6 16 fff7 16 fff8 16 fff9 16 fffa 16 fffb 16 fffc 16 fffd 16 fffe 16 ffff 16 h l h l h l h l h l h l h l v sync interrupt f(x in )/4096 interrupt timer 4 interrupt int1 interrupt int2 interrupt crt interrupt reset interrupt vector table ffde 16 ffdf 16 ffe0 16 ffe5 16 ffe8 16 ffe9 16 ffea 16 ffeb 16 ffec 16 ffed 16 ffee 16 ffef 16 h l h l h l h l h l brk instruction interrupt internal rom area serial i/o interrupt timer 1 interrupt timer 3 interrupt timer 2 interrupt internal rom area internal rom area the low-order 8 bits and the high-order 8 bits of jump destination address when an interrupt occurs, are stored to addresses l and h respectively. ffe4 16 h l int3 interrupt ffe6 16 ffe7 16 h l multi-master i c-bus interface interrupt 2 interrupt request bits are set to 1 by occurrence of an interrupt request, even if the interrupt is disabled. therefore, to disable interrupt processing, clear the interrupt request bit to 0 immediately before the interrupt disable state is cancelled (interrupt enable state, i.e., the interrupt enable bit = 1 and the interrupt disable flag = 0). tm4e tm1e it2e tm3e it1e vsce mse s1e tm2e reset crte reset interrupt request bit interrupt enable bit interrupt disable flag (i) interrupt vector crtr tm4r tm1r it2r tm3r it1r vscr msr s1r tm2r ffe9 16 , ffe8 16 ffeb 16 , ffea 16 ffed 16 , ffec 16 ffef 16 , ffee 16 fff1 16 , fff0 16 fff3 16 , fff2 16 fff5 16 , fff4 16 fff9 16 , fff8 16 fffb 16 , fffa 16 fffd 16 , fffc 16 ffff 16 , fffe 16 ffdf 16 , ffde 16 brk note: indicates to operate together. iice it3e iicr it3r ffe5 16 , ffe4 16 ffe7 16 , ffe6 16 crt interrupt int2 interrupt int1 interrupt timer 4 interrupt f(x in )/4096 interrupt v sync interrupt timer 3 interrupt timer 2 interrupt timer 1 interrupt serial i/o interrupt multi-master i 2 c-bus interface interrupt int3 interrupt brk instruction interrupt fig. 2.5.10 interrupt vector table fig. 2.5.9 interrupt control system
7220 group users manual functional description 2.6 timers 2.6 timers m37221m6-xxxsp/fp has four 8-bit timers with reload latch. figure 2.6.1 shows the timer block diagram. fig. 2.6.1 timer 1, timer 2, timer 3, and timer 4 block diagram timer 1 (8) 1/4096 1/2 1/8 timer 1 latch (8) 8 8 8 t12m0 t12m2 t12m4 t12m1 t12m3 timer 2 (8) timer 2 latch (8) 8 8 8 timer 3 (8) timer 3 latch (8) 8 8 8 timer 4 (8) timer 4 latch (8) 8 8 8 data bus timer 1 interrupt request timer 2 interrupt request t34m0 t34m2 t34m5 t34m4 t34m3 t34m1 x in p2 4 /tim2 p2 3 /tim3 selection gate : connected to black side at reset t12m : timer 12 mode register t34m : timer 34 mode register ff 16 07 16 h sync reset stp instruction timer 3 interrupt request timer 4 interrupt request notes 1: high pulse width of external clock inputs tim2 and tim3 needs 4 machine cycles or more. 2: when the external clock source is selected, timers 2 and 3 are counted at a rising edge of input signal. 3: in the stop mode or the wait mode, external clock inputs tim2 and tim3 cannot be used. (note 3) (note 3)
7220 group users manual functional description 2.6 timers 2.6.1 timer functions there are four timers; timer 1, timer 2, timer 3, timer 4 and each timer has an 8-bit reload latch. all timers are the count-down type, and when the timer latch value is n, the divide ratio is 1/(n+1)(n = 0 to 255). when the valve n is written to reload latch, is also set n to its timer, simultaneously. timer value is counted down each rising edge of count source. the timer overflows at the count next pulse, after the count value reaches 00 16 , and the interrupt request occurs. at the same time of timer overflow, the reload latch value n is set (reload) to timer, and timer continues to count down. the divide ratio is 1/(n+1). make sure that set n in the range 00 16 to ff 16 . count source timer overflow signal interrupt request writing value nn 16 nn 16 -1 00 16 01 16 nn 16 -1 nn 16 fig. 2.6.2 timer overflow timing (1) timer 1 timer 1 can select one of the following count sources: l f(x in )/16 l f(x in )/4096 (this is a clock by f(x in )/4096 interrupt and is valid only when pwm count source is supplied.) the count source of timer 1 is selected by setting bit 0 of the timer 12 mode register (address 00f4 16 ). timer 1 interrupt request occurs at timer 1 overflow. (2) timer 2 timer 2 can select one of the following count sources: l f(x in )/16 l timer 1 overflow signal l external clock from pin p2 4 /tim2 the count source of timer 2 is selected by setting bits 4 and 1 of the timer 12 mode register (address 00f4 16 ). when timer 1 overflow signal is a count source for timer 2, timer 1 functions as an 8-bit prescaler. timer 2 interrupt request occurs at timer 2 overflow.
7220 group users manual functional description 2.6 timers b7 b6 b5 b4 b3 b2 b1 b0 timer 12 mode register (t12m) [address 00f4 16 ] b after reset w timer 12 mode register 0 1 2 3 4 5 0 name functions timer 1 count source selection bit (t12m0) 0: f(x in )/16 1: f(x in )/4096 timer 2 count source selection bit (t12m1) 0: internal clock 1: external clock from p2 4 /tim2 pin timer 1 count stop bit (t12m2) 0: count start 1: count stop timer 2 count stop bit (t12m3) 0: count start 1: count stop timer 2 internal count source selection bit (t12m4) 0: f(x in )/16 1: timer 1 overflow fix this bit to 0. r 0 0 0 0 0 0 6,7 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. w r w r w r w r w r w r r fig. 2.6.3 timer 12 mode register (address 00f4 16 ) (3) timer 3 timer 3 can select one of the following count sources: l f(x in )/16 l external clock from pin h sync l external clock from pin p2 3 /tim3 the count source of timer 3 is selected by setting bits 5 and 0 of the timer 34 mode register (address 00f5 16 ) timer 3 interrupt request occurs at timer 3 overflow. (4) timer 4 timer 4 can select one of the following count sources: l f(x in )/16 l f(x in )/2 l timer 3 overflow signal the count source of timer 3 is selected by setting bits 4 and 1 of the timer 34 mode register (address 00f5 16 ). when timer 3 overflow signal is a count source for timer 4, timer 3 functions as an 8-bit prescaler. timer 4 interrupt request occurs at timer 4 overflow.
7220 group users manual functional description 2.6 timers contents timer 1 (tm1) timer 2 (tm2) timer 3 (tm3) timer 4 (tm4) timer 12 mode register (t12m) timer 34 mode register (t34m) table 2.6.1 memory map of timer-related registers addresses 00f0 16 00f1 16 00f2 16 00f3 16 00f4 16 00f5 16 b7 b6 b5 b4 b3 b2 b1 b0 timer 34 mode register (t34m) [address 00f5 16 ] b after reset rw timer 34 mode register 0 1 2 3 6,7 0 name functions timer 3 count source selection bit (t34m0) 0: f(x in )/16 1: external clock timer 4 internal count source selection bit (t34m1) 0: timer 3 overflow 1: f(x in )/16 timer 3 count stop bit (t34m2) 0: count start 1: count stop timer 4 count stop bit (t34m3) 0: count start 1: count stop nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 0 0 0 4 timer 4 count source selection bit (t34m4) 0: internal clock 1: f(x in )/2 0 5 timer 3 external count source selection bit (t34m5) 0: external clock from p2 3 /tim3 pin 1: external clock from h sync pin 0 rw rw rw rw rw rw r fig. 2.6.4 timer 34 mode register (address 00f5 16 )
7220 group users manual functional description 2.6 timers fig. 2.6.5 example of timer system 0 1 t12m4 1 t12m4 0 t12m4 0 t12m4 0 0 1 timer 2 f(x in ) t12m2 timer 1 interrupt request 1/16 timer 1 timer 2 interrupt request t12m0 t12m1 0 0 t12m0 t12m1 1 0 timer 1 interrupt request f(x in ) timer 2 interrupt request f(x in ) timer 2 timer 2 f(x in ) timer 1 interrupt request 1/16 timer 1 timer 2 interrupt request t12m0 t12m1 0 1 p2 4 /tim2 timer 2 f(x in ) timer 1 interrupt request 1/16 timer 1 timer 2 interrupt request t12m0 t12m1 0 0 1/16 0 1 t12m2 t12m3 0 1 t12m3 0 1 t12m2 0 1 t12m3 0 1 t12m2 0 1 t12m3 timer 1 1/4096
7220 group users manual functional description 2.6 timers 2.6.2 timer 3 and timer 4 when reset and when executing the stp instruction timers 3 and 4 start counting down immediately after reset status is released or stop mode is released, and cpu starts operating by supplying the internal clock f at overflow of these timers. therefore, the program can start under a stable clock. (1) when reset when reset, timers 3 and 4 are automatically set by hardware as shown in table 2.6.2, and immediately start counting down. the counting is continued, then, timer 4 overflows and the internal clock f is supplied (the internal reset is released). the program can start again. (2) when executing the stp instruction immediately after the stp instruction is executed, timers 3 and 4 are automatically set as shown in table 2.6.2 as in the case of reset and placed in the stop mode. when the stop mode is entered, the processor stops supplying the internal clock f , and contents of timers 3 and 4 are retained. when the stop mode is released by reset input or external interrupt input, the processor simultaneously supplies f(x in ), and timers 3 and 4 start counting down. the counting is continued, then, when timer 4 overflows and the internal clock f is supplied. the program can start again. table 2.6.2 contents of timers 3 and 4 when reset or when executing stp instruction timer 4 07 16 timer 3 overflow signal contents value count source note: when executing the stp instruction, f(x in )/16 is not automatically selected as the timer 3 count source. accordingly, set bit 0 of the timer 34 mode register (address 00f5 16 ) to 0 before executing the stp instruction select (f(x in )/16 is selected as the timer 3 count source). timer 3 ff 16 f(x in )/16 (except when executing the stp instructions)
7220 group user? manual functional description 2.7 serial i/o 2.7 serial i/o the m37221m6-xxxsp/fp has on-chip clock synchronous serial i/o which can receive and transmit 8-bit data serially. because pin s out also can be used as the serial i/o data input pin, it can transmit and receive with only one signal line. 2.7.1 structure of serial i/o serial i/o consists of l serial i/o register l serial i/o mode register l serial i/o counter l clock source generating counter the serial i/o register is the register which 8-bit transfer data is written into. each function of serial i/o can be controlled by setting appropriate values to the serial i/o mode register. serial i/o transfers data to and from the internal cpu via the data bus, and it transfers data to and from external devices via ports p2 2 ?2 0 . when using the serial i/o, ports p2 2 ?2 0 have the following functions: l p2 0 : serial i/o synchronous clock input/output pin (s clk ) l p2 1 : serial i/o data input/output pin (s out ) l p2 2 : serial i/o data input pin (s in ) the functions of these ports can be selected by the serial i/o mode register. the transfer clock that determines the serial data transfer rate can selected 4 kinds of clock sources with the serial i/o mode register. figure 2.7.1 shows the serial i/o block diagram, figure 2.7.2 shows the serial i/o mode register.
7220 group user? manual functional description 2.7 serial i/o fig. 2.7.1 serial i/o block diagram fig. 2.7.2 serial i/o mode register (address 00dc 16 ) 8 serial i/o shift register (8) data bus serial i/o interrupt request selection gate : connected to black side at reset. synchronous circuit frequency divider 1/8 1/4 1/16 sm1 sm0 serial i/o counter (8) sm5 : lsb msb s sm2 1/2 sm6 x in p2 2 /s in p2 1 /s out p2 0 /s clk 1/2 sm3 p2 1 latch p2 0 latch sm3 (address 00dd 16 ) sm : serial i/o mode register clock source generating circuit note: when the data is set in the serial i/o register (address 00dd 16 ), the register functions as the serial i/o shift register. b7 b6 b5 b4 b3 b2 b1 b0 serial i/o mode register (sm) [address 00dc 16 ] b name functions after reset rw serial i/o mode register 0, 1 internal synchronous clock selection bits (sm0, sm1) b1 b0 0 0: f(x in )/4 0 1: f(x in )/16 1 0: f(x in )/32 1 1: f(x in )/64 2 synchronous clock selection bit (sm2) 3 serial i/o port selection bit (sm3) 4 5 transfer direction selection bit (sm5) 7 0 0 0: p2 0 , p2 1 functions as port 1: s clk , s out 0: external clock 1: internal clock 0: lsb first 1: msb first nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is ?. 6 fix this bit to ?. 0 0 0 0 0 0 serial input pin selection bit (sm6) 0: input signal from s in pin 1: input signal from s out pin rw rw rw rw rw rw r
7220 group user? manual functional description 2.7 serial i/o bit 0 0 1 0 1 2.7.2 serial i/o register (address 00dd 16 ) the serial i/o register is serial-parallel conversion register used for data transfer. this register consists of 8-bit and can be used as both transmit and receive register. serial i/o register is assigned to address 00dd 16 . although data transfer is performed bit by bit, it is possible to specify whether the data is transferred beginning with most-significant-bit (msb) or least-significant-bit (lsb) by using bit 5 of the serial i/o mode register. (1) when bit 5 of the serial i/o mode register is ? l receive: data is received bit by bit beginning with the msb (bit 7) of the serial i/o register. l transmit: data is transmitted bit by bit beginning with the lsb (bit 0) of the serial i/o register. (2) when bit 5 of the serial i/o mode register is ? l receive: data is received bit by bit beginning with the lsb (bit 0) of the serial i/o register. l transmit: data is transmitted bit by bit beginning with the msb (bit 7) of the serial i/o register. 2.7.3 clock source generating circuit the clock source generating circuit can select oscillation frequency divided by 4, 16, 32, and 64 as the internal clock. also, it can select an external clock (the external clock is selected immediately after reset). bit 2 of the serial i/o mode register specifies internal clock or external clock. when bit 2 of the serial i/o mode register is set to ?,?an external clock is selected, when ?,?an internal clock is selected. when selecting an internal clock, set the division of oscillation frequency by bits 0 and 1 of the serial i/o mode register. l oscillation frequency divided by 4: set both bits 1 and 0 to ?. l oscillation frequency divided by 16: set bit 1 = ??and bit 0 = ?. l oscillation frequency divided by 32: set bit 1 = ??and bit 0 = ?. l oscillation frequency divided by 64: set both bit 1 and 0 to ?. the contents of bits 0 and 1 of the serial i/o mode register are invalid, when selecting an external clock. 2.7.4 serial input/output common transmission/reception mode pin p2 1 /s out can also be used as the serial i/o data input pin when the serial input pin selection bit (bit 6 of the serial i/o mode register; address 00dc 16 ) is set to ?.?(it is not necessary to set the corresponding bit of port p2 direction register to input mode.) with this function, pin p2 2 /s in can also be used as general-purpose input port p2 2 . serial i/o clock external clock internal clock serial i/o mode register bit 2 0 1 bit 1 0 0 1 1 table 2.7.1 clock source selection f(x in )/4 f(x in )/16 f(x in )/32 f(x in )/64 0 or 1 (invalid) fig. 2.7.3 serial input/output common transfer mode block diagram serial i/o register (8) clock transmit mode receive mode port p2 2 data sm6 p2 2 /s in p2 1 /s out p2 0 /s clk ? ? input or output sm: serial i/o register note: to start receiving, set ?f 16 ?to the serial i/o register
7220 group user? manual functional description 2.7 serial i/o 2.7.5 serial i/o data receive method (when an internal clock is selected) (1) initialization first, set the serial i/o mode register (address 00dc 16 ) as follows. select the synchronous clock (sm2 = ?,?sm1, sm0). set p2 0 as pin s clk (sm3 = ??. pin p2 1 /s out is not used when receiving serial data. however, since the serial i/o port selection bit (sm3) is also used for setting pin s out , port p2 1 is automatically set as pin s out and loses its general-purpose i/o port function. a select the serial input pin by the serial input pin selection bit (sm6). when sm6 = ?,?signal is input from pin p2 2 /s in ; when sm6 = ?,?signal is input from pin p2 1 /s out . when pin p2 2 /s in is a input pin, set the port p2 direction register to input mode (??. for pins p2 0 /s clk and p2 1 /s out , the corresponding bits of the port p2 direction register are automatically set by setting the serial i/o mode register. (2) receive enable state after the above setting have been made, write ?f 16 ?to the serial i/o register (address 00dd 16 ). the serial i/o counter is then set to ?7 16 ?during the write cycle and receive is enabled. (3) receive operation the data from the serial i/o data input pins (s out or s in ) is received one bit at a time into the serial i/o register in synchronization with rising edges of the transfer clock. receive operation is performed according to bit 5 (sm5) of the serial i/o mode register: when sm5 is set to ?,?data is received from msb (bit 7) of the register and shifted to the right (to low-order bit) every time new data is received. when sm5 is set to ?,?data is received from lsb (bit 0) of the register and shifted to the left (to high-order bit) every time new data is received. when all 8-bit data have been received, the serial i/o interrupt request bit (bit 2) of the interrupt request register 2 (address 00fd 16 ) is set to ?. fig. 2.7.4 serial i/o register when receiving (when sm5 = ?? transfer clock serial i/o register msb lsb d 0 d 1 d 0 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 when receiving note: to start receiving, set ?f 16 ?to the serial i/o register.
7220 group user? manual functional description 2.7 serial i/o fig. 2.7.5 serial i/o register when transmitting (when sm5 = ?? 2.7.6 serial i/o data transmit method (when an external clock is selected) (1) initialization first, set the serial i/o mode register (address 00dc 16 ) as follows. select the synchronous clock (sm2 = ??. set p2 0 as pin s clk (sm3 = ??. since the serial i/o port selection bit (sm3) is also used for the setting pin s out , port p2 1 is automatically becomes the s out pin. note: it is not necessary to set pin p2 2 /s in as pin s in when transmitting. it can be used as general- purpose input pin. (2) transmit enable state when transmit data are written to the serial i/o register, the serial i/o counter is set to ?7 16 ?and transmit is enabled. (3) transmit operation when transmit is enabled (the serial i/o counter value = ?7 16 ?, simultaneously, the data of the serial i/o register is transmitted from pin p2 1 /s out in synchronization with a falling edge of the transfer clock. transmission is performed according to bit 5 (sm5) of the serial i/o mode register: when sm5 is set to ?,?data is transmitted from lsb (bit 0) of the register and shifted to the right (to low-order bit) every time new data is transmitted. when sm5 is set to ?,?data is transmitted from msb (bit 7) of the register and shifted to the left (to high-order bit) every time new data is transmitted. when all 8-bit data have been transmitted, the serial i/o interrupt request bit (bit 2) of the interrupt request register 2 (address 00fd 16 ) is set to ?. pin p2 1 /s out will be in after transmit operation has been completed. note: on programming, note that the serial i/o counter is set even by writing to the serial i/o register with bit management instructions, such as seb and clb . d 7 d 2 d 1 d 0 transfer clock serial i/o register msb lsb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 7 d 6 d 5 d 4 d 3 when transmitting
7220 group user? manual functional description 2.7 serial i/o fig. 2.7.6 timing diagram of serial i/o 2.7.7 note when selecting a synchronous clock regardless of either an internal or external clock is selected as the serial i/o synchronous clock source, the interrupt request bit is set to ??after 8 transfer clocks. however, the serial i/o register contents will continue to be shifted as long as the transfer clock is being input to the serial i/o circuit, so it is necessary to stop after 8 transfer clocks. when an internal clock is selected, the transfer clock stops automatically after 8 clocks. when an external clock is selected, control the transfer clock externally. moreover, use an external clock of 1 mhz or less with a duty cycle of 50 %. when selecting an external clock as the synchronizing clock, write transmit data to the serial i/o register transfer clock input level is high figure 2.7.6 shows the serial i/o timing. d 0 synchronous clock transfer clock serial i/o register writing signal serial i/o output s out serial i/o input s in interrupt request bit is set to ? d 1 d 2 d 3 d 4 d 5 d 6 d 7 note: when an internal clock is selected, pin s out is at high-impedance after transfer is completed.
7220 group user? manual functional description 2.7 serial i/o the transmit side in figure 2.7.7, p2 1 is set as the serial i/o data output pin and p2 0 is set as the serial i/o synchronous clock output pin by the initialization program. the receive side, p2 1 is set as the serial i/o data input pin and p2 0 is used for the serial i/o synchronous clock (external clock) input pin by the initialization program. figure 2.7.8 shows the serial data transmit/receive processing sequence using the above structure. fig. 2.7.7 connection example for serial i/o transmit/receive as a result of the above processing 1-byte data is transferred from the transmit side to the receive side. when the transmit operation is completed, interrupts occur on both sides, so that completion of the data transfer can be reported. after that, repeating the processing after the symbol ( t ) can transmit/receive more data. transmit side ldm #$0c, $dc ; set serial i/o mode register. clb 2, $fd ; reset serial i/o interrupt request bit. seb 2, $ff ; set the serial i/o interrupt enable bit to ?. ldm #data, $dd ; write transfer data to serial i/o register. fig. 2.7.8 serial data transmit/receive processing sequence receive side ldm #$48, $dc ; set serial i/o mode register. clb 2, $fd ; reset serial i/o interrupt request bit. seb 2, $ff ; set serial i/o interrupt enable bit to ?. t ldm #$ff, $dd ; write dummy data to serial i/o register. serial i/o mode register serial data p2 1 /s out s out /p2 1 p2 0 /s clk s clk /p2 0 synchronous clock transmit side receive side serial i/o mode register m37221m6-xxxsp/fp m37221m6-xxxsp/fp 1 1 b0 b7 0 1: s clk , s out internal synchronous clock selection bits serial i/o port selection bit fix this bit to ?. transfer direction selection bit serial input pin selection bit nothig is assigned. synchronous clock selection bit 1: internal clock 1 b0 b7 0 0 1: s clk , s out 0: external clock 1: input signal from s out pin 1 internal synchronious clock selection bits serial i/o port selection bit fix this bit to ?. transfer direction selection bit serial input pin selection bit nothig is assigned. synchronous clock selection bit
7220 group users manual functional description 2.8 multi-master i 2 c-bus interface 2.8 multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a serial communications circuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both an arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. figure 2.8.1 shows a block diagram of the multi-master i 2 c-bus interface and table 2.8.1 shows multi- master i 2 c-bus interface functions. the m37220 m3-xxsp/fp does not have this function. table 2.8.1 multi-master i 2 c-bus interface functions item format communication mode scl clock frequency function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at f = 4 mhz) f : system clock = f(x in )/2 note: we are not responsible for any third partys infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the i 2 c control register at address 00da 16 ) for connections between the i 2 c-bus interface and ports (scl1, scl2, sda1, sda2).
7220 group users manual functional description 2.8 multi-master i 2 c-bus interface i c address register b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 rbw noise elimination circuit serial data (sda) address comparator b7 i c data shift register b0 data control circuit system clock ( f ) interrupt generating circuit interrupt request signal (iicirq) b7 mst trx bb pin al aas ad0 lrb b0 i c status register s1 b7 b0 bsel1 bsel0 10bit sad als bc2 bc1 bc0 s1d bit counter bb circuit clock control circuit noise elimination circuit serial clock (scl) b7 b0 ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 internal data bus clock division s0 s2 s0d al circuit eso 2 2 i c clock control register 2 2 i c control register 2 fig. 2.8.1 block diagram of multi-masteer i 2 c-bus interface 2.8.1 construction of multi-master i 2 c-bus interface the multi-master i 2 c-bus interface consists of the following : l i 2 c address register l i 2 c data shift register l i 2 c clock control register l i 2 c control register l i 2 c status register l other control circuits the data transfer with the internal cpu is performed via data bus, the data transfer with an external device is performed via ports p1 1 Cp1 4. when using multi-master i 2 c-bus interface, these ports p1 1 Cp1 4 are assigned to the following functions. l p1 1 : multi-master i 2 c-bus interface synchronous clock input/output pin 1 (scl1) l p1 2 : multi-master i 2 c-bus interface synchronous clock input/output pin 2 (scl2) l p1 3 : multi-master i 2 c-bus interface data input/output pin 1 (sda1) l p1 4 : multi-master i 2 c-bus interface data input/output pin 2 (sda2) the shift clock to determine the transfer speed of serial data is selected by the i 2 c clock control register (refer to figure 2.8.4 ). a serial data and a serial clock is referred as sda, scl respectively, hereafter.
7220 group users manual 2.8 multi-master i 2 c-bus interface 2.8.2 multi-master i 2 c-bus interface-related registers (1) i 2 c data shift register (s0: address 00d7 16 ) the i 2 c data shift register (s0 : address 00d7 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. the i 2 c data shift register is in a write enable status only when the eso bit of the i 2 c control register (address 00da 16 ) is 1. the bit counter is reset by a write instruction to the i 2 c data shift register. when both the eso bit and the mst bit of the i 2 c status register (address 00f9 16 ) are 1, the scl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift register is always enabled regardless of the eso bit value. figure 2.8.2 shows the i 2 c data shift register. fig. 2.8.2 i 2 c data shift register b7 b6 b5 b4 b3 b2 b1 b0 i c data shift register (s0) [address 00d7 16 ] b functions after reset rw i c data shift register 0 to 7 this is an 8-bit shift register to store receive data and write transmit data. indeterminate 2 2 note: 2 to write data into the i c data shift register after setting the mst bit to 0 (slave mode), keep an interval of 8 machine cycles or more. name d0 to d7 rw functional description
7220 group users manual functional description 2.8 multi-master i 2 c-bus interface (2) i 2 c address register (s0d: address 00d8 16 ) the i 2 c address register (address 00d8 16 ) consists of a 7-bit slave address and a read/write bit. in the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the start condition are detected. n bit 0: read/write bit (rbw) not used when comparing addresses, in the 7-bit addressing mode. in the 10-bit addressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rbw) of the i 2 c address register. the rbw bit is cleared to 0 automatically when the stop condition is detected. n bits 1 to 7: slave address (sad0Csad6) these bits store slave addresses. regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits. figure 2.8.3 shows the i 2 c address register. fig. 2.8.3 i 2 c address register b7 b6 b5 b4 b3 b2 b1 b0 0 read/write bit (rbw) 1 to 7 slave address (sad0 to sad6) 0: read 1: write 0 0 the address data transmitted from the master is compared with the contents of these bits. i 2 c address register i 2 c address register (s0d) [address 00d8 16 ] b name functions after reset rw rw rw
7220 group users manual 2.8 multi-master i 2 c-bus interface (3) i 2 c clock control register (s2: address 00db 16 ) the i 2 c clock control register (address 00db 16 ) is used to set ack control, scl mode and scl frequency. n bits 0 to 4: scl frequency control bits (ccr0Cccr4) these bits control the scl frequency. refer to table 2.8.4. n bit 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to 0, the standard clock mode is set. when the bit is set to 1, the high-speed clock mode is set. n bit 6: ack bit (ack bit) this bit sets the sda status when an ack clock ] is generated. when this bit is set to 0, the ack return mode is set and sda goes to low at the occurrence of an ack clock. when the bit is set to 1, the ack non-return mode is set. the sda is held in the high status at the occurrence of an ack clock. however, when the slave address matches the address data in the reception of address data at ack bit = 0, the sda is automatically made low (ack is returned). if there is a mismatch between the slave address and the address data, the sda is automatically made high (ack is not returned). ] ack clock: clock for acknowledgment n bit 7: ack clock bit (ack) this bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. when this bit is set to 0, the no ack clock mode is set. in this case, no ack clock occurs after data transmission. when the bit is set to 1, the ack clock mode is set and the master generates an ack clock upon completion of each 1-byte data transmission. the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (make sda high) and receives the ack bit generated by the data receiving device. figure 2.8.4 shows the i 2 c clock control register. note: do not write data into the i 2 c clock control register during transmission. if data is written during transmission, the i 2 c clock generator is reset, so that data cannot be transmitted normally. functional description
7220 group users manual functional description 2.8 multi-master i 2 c-bus interface fig. 2.8.4 i 2 c clock control register b7 b6 b5 b4 b3 b2 b1 b0 i 2 c clock control register (s2 : address 00db 16 ) i 2 c clock control register 0 to 4 scl frequency control bits (ccr0 to ccr4) 7 5 6 scl mode specification bit (fast mode) 0 : standard clock mode 1 : high-speed clock mode 0 standard clock mode b name functions after reset rw 0 0 0 ack bit (ack bit) ack clock bit (ack) 0 : ack is returned. 1 : ack is not returned. 0 : no ack clock 1 : ack clock high speed clock mode setup disabled setup disabled 00 to 02 setup disabled 333 03 setup disabled 250 04 100 400 (see note) 05 83.3 166 06 500/ccr value 1000/ccr value ... 17.2 34.5 1d 16.6 33.3 1e 16.1 32.3 1f (at f = 4 mhz, unit : khz) note: at 4000khz in the high-speed clock mode, the duty is as below . 0 period : 1 period = 3 : 2 in the other cases, the duty is as below. 0 period : 1 period = 1 : 1 setup value of ccr4Cccr0 rw rw rw rw
7220 group users manual 2.8 multi-master i 2 c-bus interface (4) i 2 c control register (s1d: address 00da 16 ) the i 2 c control register (address 00da 16 ) controls the data communication format. n bits 0 to 2: bit counter (bc0Cbc2) these bits decide the number of bits for the next 1-byte data to be transmitted. an interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. when a start condition is received, these bits become 000 2 and the address data is always transmitted and received in 8 bits. n bit 3: i 2 c-bus interface use enable bit (eso) this bit enables usage of the multi-master i 2 c-bus interface. when this bit is set to 0, the use disable status is provided, so the sda and the scl become high-impedance. when the bit is set to 1, use of the interface is enabled. when eso = 0, the following is performed. ? pin = 1, bb = 0 and al = 0 are set (they are bits of the i 2 c status register at address 00f8 16 ). ? writing data to the i 2 c data shift register (address 00d7 16 ) is disabled. n bit 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to 0, the addressing format is selected, so that address data is recognized. when a match is found between a slave address and address data as a result of comparison or when a general call (refer to (5) i 2 c status register, bit 1) is received, transmission processing can be performed. when this bit is set to 1, the free data format is selected, so that slave addresses are not recognized. n bit 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to 0, the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address register (address 00d8 16 ) are compared with address data. when this bit is set to 1, the 10-bit addressing format is selected, all the bits of the i 2 c address register are compared with address data. n bit 6 and 7: connection control bits between i 2 c-bus interface and ports (bsel0, bsel1) this bits controls the connection between scl and ports or sda and ports. when using the ports as multi-master i 2 c-bus interface, set the corresponding bits of port p1 direction register to 1 (output mode). figure 2.8.5 shows the connection port control by bsel0 and bsel1, figure 2.8.6 shows the i 2 c control register. fig. 2.8.5 connection port control by bsel0 and bsel1 0 1 bsel0 scl1/p1 1 scl2/p1 2 0 1 bsel1 0 1 bsel0 sda1/p1 3 sda2/p1 4 0 1 bsel1 multi-master i 2 c-bus interface scl sda functional description
7220 group users manual functional description 2.8 multi-master i 2 c-bus interface fig. 2.8.6 i 2 c control register b7 b6 b5 b4 b3 b2 b1 b0 0 to 2 bit counter (number of transmit/recieve bits) (bc0 to bc2) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 3 i 2 c-bus interface use enable bit (eso) 0 : disabled 1 : enabled 4 data format selection bit (als) 0 : addressing mode 1 : free data format 5 addressing format selection bit (10bit sad) 0 : 7-bit addressing format 1 : 10-bit addressing format 6, 7 connection control bits between i c-bus interface and ports (bsel0, bsel1) b7 b6 connection port 0 0 : none 0 1 : scl1, sda1 1 0 : scl2, sda2 1 1 : scl1, sda1 scl2, sda2 0 0 0 0 0 i 2 c control register (s1d : address 00da 16 ) i 2 c control register b name functions after reset rw note: when using ports p1 1 -p1 4 as i c-bus interface, the output structure changes automatically from cmos output to n-channel open-drain output. however, set the port direction register to 1 (output mode). 2 2 rw rw rw rw rw
7220 group user?s manual functional description 2.8 multi-master i 2 c-bus interface (5) i 2 c status register (s1: address 00d9 16 ) the i 2 c status register (address 00d9 16 ) controls the i 2 c-bus interface status. the low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. n bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to 0. if ack is not returned, this bit is set to 1. except in the ack mode, the last bi t value of received data is input. the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (address 00d7 16 ). n bit 1: general call detecting flag (ad0) this bit is set to 1 when a general call ] whose address data is all 0 is received in the slave mode. by a general call of the master device, every slave de vice receives control data after the general call. the ad0 bit is set to 0 by detecting the sto p condition or start condition. n bit 2: slave address comparison flag (aas) this flag indicates a comparison result of address data. in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to 1 in one of the following conditions. the address data immediately after occurrence of a start c ondition matches the slave address stored in the high-order 7 bits of the i 2 c address register (address 00d8 16 ). a general call is received. in the slave reception mode, when the 10-bit addressing form at is selected, this bit is set to 1 with the following condition. when the address data is compared with the i 2 c address register (8 bits consists of slave address and rbw), the first bytes match. a the state of this bit is changed from 1 to 0 by executin g a write instruction to the i 2 c data shift register (address 00d7 16 ). n bit 3: arbitration lost ] detecting flag (al) in the master transmission mode, when a device other than th e microcomputer sets the sda to low by any other device, arbitration is judged to have been lost, so that this bit is set to 1. at the same time, the trx bit is set to 0, so that immediatel y after transmission of the byte, whose arbitration was lost is completed, the mst bit is set to 0. when arbitration is lost during slave address transmission, the trx bit is set to 0 and the rece ption mode is set. consequently, it becomes possible to receive and recognize its own slave addr ess transmitted by another master device. ] arbitration lost: the status in which communication as a mas ter is disabled.
7220 group users manual functional description 2.8 multi-master i 2 c-bus interface n bit 4: i 2 c-bus interface interrupt request bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the state of the pin bit changes from 1 to 0. at the same time, an interrupt request signal is sent to the cpu. the pin bit is set to 0 in synchronization with a falling edge of the last clock (including the ack clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the pin bit. when the pin bit is 0, the scl is kept in the 0 state and clock generation is disabled. figure 2.8.7 shows an interrupt request signal generating timing chart. the pin bit is set to 1 in any one of the following conditions. ? executing a write instruction to the i 2 c data shift register (address 00d7 16 ). ? when the eso bit is 0 ? at reset the conditions in which the pin bit is set to 0 are shown below: ? immediately after completion of 1-byte data transmission (including when arbitration lost is detected) ? immediately after completion of 1-byte data reception ? in the slave reception mode, with als = 0 and immediately after completion of slave address or general call address reception ? in the slave reception mode, with als = 1 and immediately after completion of address data reception n bit 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to 0, this bus system is not busy and a start condition can be generated. when this bit is set to 1, this bus system is busy and the occurrence of a start condition is disabled by the start condition duplication prevention function (note). this flag can be written by software only in the master transmission mode. in the other modes, this bit is set to 1 by detecting a start condition and set to 0 by detecting a stop condition. when the eso bit of the i 2 c control register (address 00da 16 ) is 0 and at reset, the bb flag is kept in the 0 state. n bit 6: communication mode specification bit (transfer direction specification bit: trx) this bit decides the direction of transfer for data communication. when this bit is 0, the reception mode is selected and the data of a transmitting device is received. when the bit is 1, the transmission mode is selected and address data and control data are output into the sda in synchronization with the clock generated on the scl. when the als bit of the i 2 c control register (address 00f9 16 ) is 0 in the slave reception mode is selected, the trx bit is set to 1 (transmit) if the least significant bit (r/w bit) of the address data transmitted by the master is 1. when the als bit is 0 and the r/w bit is 0, the trx bit is cleared to 0 (receive). the trx bit is cleared to 0 in one of the following conditions. ? when arbitration lost is detected. ? when a stop condition is detected. ? when occurrence of a start condition is disabled by the start condition duplication prevention function (note). ? with mst = 0 and when a start condition is detected. ? with mst = 0 and when ack non-return is detected. ? at reset
7220 group users manual functional description 2.8 multi-master i 2 c-bus interface fig. 2.8.8 i 2 c status register b7 b6 b5 b4 b3 b2 b1 b0 i 2 c status register (s1) [address 00d9 16 ] i 2 c status register 0 3 4 5 6, 7 b7 b6 0 0 : slave recieve mode 0 1 : slave transmit mode 1 0 : master recieve mode 1 1 : master transmit mode 1 2 0 0 0 1 0 b name functions after reset rw communication mode specification bits (trx, mst) 0 : bus free 1 : bus busy bus busy flag (bb) 0 : interrupt request issued 1 : no interrupt request issued i 2 c-bus interface interrupt request bit (pin) 0 : not detected 1 : detected arbitration lost detecting flag (al) (see note) 0 : address mismatch 1 : address match slave address comparison flag (aas) (see note) 0 : no general call detected 1 : general call detected general call detecting flag (ad0) (see note) 0 : last bit = 0 1 : last bit = 1 last receive bit (lrb) (see note) note : these bits and flags can be read out, but cannnot be written. indeterminate r r r r rw rw 0 rw scl pin iicirq n bit 7: communication mode specification bit (master/slave specification bit: mst) this bit is used for master/slave specification for data communication. when this bit is 0, the slave is specified, so that a start condition and a stop condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. when this bit is 1, the master is specified and a start condition and a stop condition are generated, and also the clocks required for data communication are generated on the scl. the mst bit is cleared to 0 in one of the following conditions. ? immediately after completion of 1-byte data transmission when arbitration lost is detected ? when a stop condition is detected. ? when occurrence of a start condition is disabled by the start condition duplication preventing function (note). ? at reset figure 2.8.7 shows the interrupt request signal generating timing, figure 2.8.8 shows the i 2 c status register. note: the start condition duplication prevention function disables the start condition generation, reset of bit counter reset, and scl output when the following condition is satisfied: a start condition is set by another master device. fig. 2.8.7 interrupt request signal generating timing
7220 group users manual functional description 2.8 multi-master i 2 c-bus interface (1) start condition generation method when the eso bit of the i 2 c control register (address 00da 16 ) is 1, execute a write instruction to the i 2 c status register (address 00d9 16 ) to set the mst, trx and bb bits to 1. a start condition will then be generated. after that, the bit counter becomes 000 2 and an scl for 1 byte is output. the start condition generating timing and bb bit set timing are different in the standard clock mode and the high-speed clock mode. refer to figure 2.8.9 for the start condition generation timing diagram, and table 2.8.2 for the start condition/stop condition generation timing table. (2) stop condition generation method when the eso bit of the i 2 c control register (address 00da 16 ) is 1, execute a write instruction to the i 2 c status register (address 00d9 16 ) for setting the mst bit and the trx bit to 1 and the bb bit to 0. a stop condition will then be generated. the stop condition generation timing and the bb flag reset timing are different in the standard clock mode and the high-speed clock mode. refer to figure 2.8.10 for the stop condition generating timing diagram, and table 2.8.2 for the start condition/stop condition generation timing table. 2.8.3 start condition, stop condition generation method fig. 2 .8.9 start condition generation timing diagram i 2 c status register write signal set time for bb flag hold time setup time scl sda bb flag setup time fig. 2 .8.10 stop condition generation timing diagram i 2 c status register write signal reset time for bb flag hold time setup time scl sda bb flag item setup time hold time set/reset time for bb flag high-speed clock mode 2.5 s (10 cycles) 2.5 s (10 cycles) 1.5 s (6 cycles) standard clock mode 5.0 s (20 cycles) 5.0 s (20 cycles) 3.0 s (12 cycles) note: absolute time at f = 4 mhz. the value in parentheses denotes the number of f cycles. table 2.8.2 start condition/stop condition generation timing table
7220 group users manual 2.8 multi-master i 2 c-bus interface (3) start/stop condition detect conditions the start/stop condition detect conditions are shown in figure 2.8.11 and table 2.8.3. only when the 3 conditions of table 10 are satisfied, a start/stop condition can be detected. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal iicirq is generated to the cpu. hold time setup time scl sda (start condition) sda (stop condition) scl release time hold time setup time fig. 2.8.11 start condition/stop condition detect timing diagram table 2.8.3 start condition/stop condition detect conditions standard clock mode 6.5 s (26 cycles) < scl release time 3.25 s (13 cycles) < setup time 3.25 s (13 cycles) < hold time high-speed clock mode 1.0 s (4 cycles) < scl release time 0.5 s (2 cycles) < setup time 0.5 s (2 cycles) < hold time note: absolute time at f = 4 mhz. the value in parentheses denotes the number of f cycles. functional description
7220 group users manual functional description 2.8 multi-master i 2 c-bus interface (4) address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective address communication formats is described below. 7-bit addressing format to meet the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00da 16 ) to 0. the first 7-bit address data transmitted from the master is compared with the high- order 7-bit slave address stored in the i 2 c address register (address 00d8 16 ). at the time of this comparison, address comparison of the rbw bit of the i 2 c address register (address 00d8 16 ) is not made. for the data transmission format when the 7-bit addressing format is selected, refer to figure 2.8.12, (1) and (2). 10-bit addressing format to meet the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00da 16 ) to 1. an address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the i 2 c address register (address 00d8 16 ). at the time of this comparison, an address comparison between the rbw bit of the i 2 c address __ register (address 00d8 16 ) and the r/w bit which is the last bit of the address data transmitted from __ the master is made. in the 10-bit addressing mode, the r/w bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. when the first-byte address data matches the slave address, the aas bit of the i 2 c status register (address 00d9 16 ) is set to 1. after the second-byte address data is stored into the i 2 c data shift register (address 00d7 16 ), make an address comparison between the second-byte data and the slave address by software. when the address data of the 2nd byte matches the slave address, set the rbw bit of the i 2 c address register (address 00d8 16 ) to 1 by software. this processing can __ match the 7-bit slave address and r/w data, which are received after a restart condition is detected, with the value of the i 2 c address register (address 00d8 16 ). for the data transmission format when the 10-bit addressing format is selected, refer to figure 2.8.12, (3) and (4). s slave address a data a data a/a p r/w 7 bits 0 1 to 8 bits 1 to 8 bits s slave address a data a data ap 7 bits 1 1 to 8 bits 1 to 8 bits (1) a master-transmitter transmits data to a slave-receiver s slave address 1st 7 bits a a data 7 bits 0 8 bits 1 to 8 bits (2) a master-receiver receives data from a slave-transmitter slave address 2nd byte a data a/a p 1 to 8 bits s slave address 1st 7 bits a a 7 bits 0 8 bits 7 bits (3) a master-transmitter transmits data to a slave-receiver with a 10-bit address slave address 2nd byte data 1 to 8 bits sr slave address 1st 7 bits a data ap 1 to 8 bits 1 (4) a master-receiver receives data from a slave-transmitter with a 10-bit address s a sr from master to slave from slave to master r/w r/w r/w r/w fig. 2.8.12 address data communication format : start condition : ack bit : restart condition p : stop condition r/w : read/write bit
7220 group users manual a-d control register 1 bits 0 to 2 comparator control data bus bit 4 switch tree a-d control register 2 resistor ladder compa- rator analog signal switch bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a-d control register 1 p1 5 /a-d1/int3 p1 6 /a-d2 p1 7 /a-d3 p0 6 /int2/a-d4 p3 0 /a-d5 p3 1 /a-d6 2.9 a-d comparator the m37221m6-xxxsp/fp has a-d comparator consists of the 6-bit d-a converter by resistance string method and a comparator. figure 2.9.1 shows the a-d comparator block diagram. fig. 2.9.1 a-d comparator block diagram the following explains a-d comparison method. set 0 to corresponding bits of the direction register to use ports as analog input pins. select the analog input pin with bits 0 to 2 of a-d control register 1 (address 00ee 16 ). a set the comparison voltage v ref for d-a conversion by bits 0 to 5 of a-d control register 2 (address 00ef 16 ). table 2.9.1 shows the v ref values corresponding to the set values above. a-d comparison starts by writing to a-d control register 2. ? this voltage comparison needs for 16 machine cycles ( nop instruction 5 8). ? the comparison result is stored in bit 4 of the a-d control register 1 (address 00ee 16 ). when the input voltage value is lower than the comparison voltage value, bit 4 is cleared to 0; when the input voltage value is higher than the comparison voltage value, bit 4 is set to 1 (refer to figure 2.9.2 ). functional description
7220 group users manual functional description 2.9 a-d comparator b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 2(ad2) [address 00ef 16 ] b after reset rw a-d control register 2 0 to 5 6, 7 0 0 name functions d-a converter set bits (adc0, adc1, adc2, adc3, adc4, adc5) b0 b1 b2 b3 b4 b5 nothing is assigned. these bits are write disable bits. when these bits are reed out, the values are 0. 1 000000 00000 0 0000 0 0 111 1 1 11111 1 111111 : 3/128vcc : 5/128vcc : 123/128vcc : 125/128vcc : 127/128vcc : 1/128vcc rw r fig. 2.9.3 a-d control register 2 (address 00ef 16 ) fig. 2.9.2 a-d control register 1 (address 00ee 16 ) table 2.9.1 relationship between contents of a-d control register 2 and reference voltage v ref a-d control register 2 bit 3 0 0 0 : 1 1 1 bit 4 0 0 0 : 1 1 1 bit 5 0 0 0 : 1 1 1 bit 2 0 0 0 : 1 1 1 bit 1 0 0 1 : 0 1 1 bit 0 0 1 0 : 1 0 1 internal analog voltage (comparison voltage v ref ) 1/128v cc 3/128v cc 5/128v cc : 123/128v cc 125/128v cc 127/128v cc b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 1 (ad1) [address 00ee 16 ] b after reset rw a-d control register 1 0 to 2 analog input pin selection bits (adm0, adm1, adm2) name functions b2 b1 b0 0 0 0 : a - d1 0 0 1 : a-d2 0 1 0 : a-d3 0 1 1 : a-d4 1 0 0 : a-d5 1 0 1 : a-d6 1 1 0 : 1 1 1 : 4 storage bit of comparison result (adm4) 0: input voltage < reference voltage 1: input voltage > reference voltage 5 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 indeterminate 0 0 do not set. 3 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. rw rw r r
7220 group users manual 2.10 pwm 2.10 pwm the m37221m6-xxxsp/fp has one 14-bit pwm (pulse width modulator) [da], and six 8-bit pwm [pwm0C pwm5]. table 2.10.1 shows the pwm function performance. table 2.10.1 pwm function performance (at oscillation frequency = 8 mhz) figure 2.10.1 shows the 14-bit pwm block diagram and figure 2.10.2 shows the 8-bit pwm block diagram. performance resolution (bits) minimum resolution bit width ( s) repeat cycle ( s) 14-bit pwm [da] 14 0.25 4096 8-bit pwm 8 4 1024 inside of with the others. 1/2 x in pwm timing generating circuit 14-bit pwm circuit pn2 pn4 pw1 da msb da-h register (address : 00ce 16 ) da latch (14 bits) da-l register (note) (address : 00cf 16 ) lsb 8 6 14 6 d-a data bus selection gate : pw: pwm output control register 1 pn: pwm output control register 2 pw0 b7 b0 connected to black side when reset. pass gate note: the da-l register also functions as the low-order 6 bits of the da latch. fig. 2.10.1 14-bit pwm (da) block diagram functional description
7220 group users manual functional description 2.10 pwm fig. 2.10.2 8-bit pwm block diagram 2.10.1 8-bit pwm registers (addresses 00d0 16 to 00d4 16 and 00f6 16 ) /da registers (addresses 00ce 16 and 00cf 16 ) data transfer from the 8-bit pwm registers (addresses 00d0 16 to 00d4 16 and 00f6 16 ) to the 8-bit pwm circuit is executed when writing data to the registers. the output signal from the 8-bit pwm output pin corresponds to the contents of this register. also, data transfer from the da registers (addresses 00ce 16 and 00cf 16 ) to the 14-bit pwm circuit is executed when writing data to the da-l register (address 00cf 16 ). the output signal from the dCa output pin corresponds to the contents of the da latch. reading from the da register (address 00ce 16 ) means the da latch contents. therefore, it is possible to confirm the data being output from the d-a output pin by reading the da register. the contents of the 8-bit pwm register and da register are indeterminate after reset. inside of with the others. pwm1 register (address : 00d1 16 ) 1/2 x in pwm timing generating circuit pwm register (address : 00d0 16 ) b7 b0 8 8-bit pwm circuit pn3 p0 0 pw2 d0 0 pwm0 p0 1 pw3 d0 1 pwm1 p0 2 pw4 d0 2 pwm2 p0 3 pw5 d0 3 pwm3 p0 4 pw6 d0 4 pwm4 p0 5 pw7 d0 5 pwm5 pwm2 register (address : 00d2 16 ) pwm3 register (address : 00d3 16 ) pwm4 register (address : 00d4 16 ) pwm5 register (address : 00f6 16 ) data bus selection gate : pw: pwm output control register 1 pn: pwm output control register 2 pw0 connected to black side when reset. is as same contents d0: port p0 direction register 16 )
7220 group users manual 2.10 pwm 2.10.2 14-bit pwm (da output) the 14-bit pwm automatically outputs a pwm rectangular waveform from the d-a pin by writing high-order 8 bits of the output data to the da-h register and the low-order 6 bits to the da-l register. data of the da-h register are transferred to the 14-bit pwm circuit when writing to the da-l register. the following explains the output operation of 14-bit pwm rectangular waveform (when f(x in ) = 8 mhz). the repeat cycle t (4,096 s) of output waveform is divided into 2 6 = 64 smaller interval t (t = 64 s). the t is further divided into the minimum resolution bit t of 2 8 = 256 ( t = 0.25 s). the high duration of the fundamental waveform is determined by the high-order 8 bits d h of the da latch. high duration (time) = t 5 d h (when f(x in ) = 8 mhz, 0.25d h s) because the d h values are 0 to 255, the high duration can be selected a total of 256. a the smaller interval t m with a longer high level area by t is specified by the low-order 6 bits d l of the da latch. the t m is specified from among 64 smaller intervals (t 0 to t 63 ). therefore, a rectangular waveform consisted of 2-kind waveforms with different high duration are output from pin dCa (a length of entirely high output cannot be output). figure 2.10.3 shows the 14-bit pwm output example, table 2.10.2 shows the relation between d l and t m (m = 0 to 63). table 2.10.2 the relation between d l and t m ( m = 0 to 63) low-order 6-bit data of da register (d l ) smaller intervals that high duration is longer by t t m ( m = 0 to 63) nothing m = 32 m = 16, 48 m = 16, 32, 48 m = 8, 24, 40, 56 m = 8, 24, 32, 40, 56 m = 8, 16, 24, 40, 48, 56 : m = 4, 12, 20, 28, 36, 44, 52, 60 : m = 2, 6, 10, 14, 18, ... 46, 50, 54, 58, 62 : m = 1, 3, 5, 7, 9 ... 55, 57, 59, 61, 63 : m = 1, 3, 5, 7, 9 ... 52, 55, 57, 59, 60, 61, 63 : m = 1 to 63 (0 is not included) number 0 1 2 3 4 5 6 : 8 : 16 : 32 : 40 : 63 msb 0 0 0 0 0 0 lsb 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 : 0 0 1 0 0 0 : 0 1 0 0 0 0 : 1 0 0 0 0 0 : 1 0 1 0 0 0 : 1 1 1 1 1 1 functional description
7220 group users manual functional description 2.10 pwm fig. 2.10.3 14-bit pwm output example (f(x in ) = 8 mhz) 0.25 m s b7 b0 b6 b5 b4 b3 b2 b1 0 0 010110 b13 b6 00 010110 b0 b5 101000 set 2c 16 to da-h register. [da-h register] d h at writing of da-l b0 b6 b5 b4 b3 b2 b1 0 10100 set 28 16 to da-l register. [da-l register] d l at writing of da-l undefined these bits decide high level area of fundamental waveform. these bits decide smaller interval tm in which high level area is [high level area of fundamental waveform + t ]. = minimum resolution bit width 0.25 m s high-order 8-bit value of da latch 5 high level area of fundamental waveform ff 00 d3 fe fd d6 d4 02 01 d5 14-bit pwm output 8-bit counter 0.25 m s 5 44 ff 00 d3 fe fd d6 d4 02 01 d5 14-bit pwm output 8-bit counter 0.25 m s 5 45 fundamental waveform waveform of smaller interval tm specified by low-order 6 bits fundamental waveform of smaller interval tm which is not specified by low-order 6 bits is not changed. 14-bit pwm output low-order 6-bit output of da latch 0.25 m s 5 44 t = 0.25 m s t = 4096 m s repeat period t 0 t 1 t 2 t 3 t 4 t 5 t 59 t 60 t 61 t 62 t 63 [da latch] b7 2c 2b 2a 03 02 01 00 2c 2b 2a 03 02 01 00
7220 group users manual 2.10 pwm 2.10.3 8-bit pwm (pwm0 to pwm5: address 00d0 16 to 00d4 16 and 00f6 16 ) the 8-bit pwm outputs waveform which is the logical sum (or) of pulses corresponding to bits 0 to 7 of the 8-bit pwm register. that is to say, 8 kinds of pulses corresponding to the weight of each bit of the 8-bit pwm register are output inside the circuit during 1 cycle. among these pulses, or of pulses that correspond to bits, which is set to 1, in the 8-bit pwm register to external devices as pwm output. figure 2.10.4 shows the pulse waveforms corresponding to the weight of each bit of the 8-bit pwm register. figure 2.10.5 shows the example of 8-bit pwm output. as shown in the figures, 256 kinds of output (high duration: 0/256 to 255/256) are selected by changing the contents of the pwm register (a length of entirely high cannot be output). functional description
7220 group users manual functional description 2.10 pwm fig. 2.10.4 pulse waveforms corresponding to weight of each bit of 8-bit pwm register fig. 2.10.5 example of 8-bit pwm output 1 3 5 7 9 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255 5 4 12 20 28 36 44 52 60 68 76 84 92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252 8 16 48 80 112 144 176 208 240 24 40 56 72 88 104 120 136 152 168 184 200 216 232 248 32 96 160 224 64 192 bit 7 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 128 bit 0 pwm output t = 4 m s t = 1024 m s f(x in ) = 8 mhz t t = 256 t ff 16 (255) 18 16 (24) 01 16 (1) 00 16 (0)
7220 group users manual 2.10 pwm 2.10.4 14-bit pwm output control how to control the 14-bit pwm output is described below. set 0 to bit 0 of pwm output control register 1 (address 00d5 16 ) to supply the pwm count source (this bit is cleared to 0 when reset). set the high-order 8 bits of the output data to the da-h register. a set the low-order 6 bits of the output data to the da-l register. ? data is written to the 14-bit pwm circuit by writing data to the da-l register. for this reason, even when changing only the high-order 8 bits of the output data, be sure to write the low-order 6 bits data to the da-l register again. conversely, when changing low-order 6 bits only, it needs to only write data to the da-l register, and needs not write the high-order 8-bit data again. ? select the output polarity by bit 2 of pwm output control register 2 (address 00d6 16 ). when setting to 0, a positive polarity is selected; when 1, a negative polarity is selected. ? 14-bit pwm is output from the d-a pin by clearing bit 1 of pwm output control register 1 to 0. when setting to 1, pin d-a functions as a 1-bit general-purpose output port. in this case, it is possible to specify either high output (= 1) or low output(= 0) output by bit 4 of pwm output control register 2. fig. 2.10.6 pwm output control register 1 (address 00d5 16 ) b7 b6 b5 b4 b3 b2 b1 b0 pwm output control register 1 (pw) [address 00d5 b after reset rw pwm output control register 1 0 1 2 3 4 0 name functions da, pwm count source selection bit (pw0) 0 : count source supply 1 : count source stop p0 0 /pwm0 output selection bit (pw2) 0: p0 0 output 1: pwm0 output p0 1 /pwm1 output selection bit (pw3) 0: p0 1 output 1: pwm1 output p0 2 /pwm2 output selection bit (pw4) 0: p0 2 output 1: pwm2 output 5 p0 3 /pwm3 output selection bit (pw5) 0: p0 3 output 1: pwm3 output 6 p0 4 /pwm4 output selection bit (pw6) 0: p0 4 output 1: pwm4 output da/pn4 output selection bit (pw1) 0 : da output 1 : pn4 output 7 p0 5 /pwm5 output selection bit (pw7) 0: p0 5 output 1: pwm5 output 0 0 0 0 0 0 0 16 ] rw rw rw rw rw rw rw rw functional description
7220 group users manual functional description 2.10 pwm 2.10.5 8-bit pwm output control how to control the 8-bit pwm output is described below. the pwm0Cpwm7 output pins are also used for port p0 0 Cp0 3 and p6 0 Cp6 3 . set 0 to bit 0 of the pwm output control register 1 (address 00d5 16 ) to supply the pwm count source (this bit is cleared to 0 after reset). write output data to the corresponding 8-bit pwm registers (addresses 00d0 16 to 00d4 16 and 00f6 16 ). a set the corresponding bit of the port p0 direction register to 1 to specify the output mode. ? select the output polarity by bit 3 of the pwm output control register 2 (address 00d6 16 ). when this bit is cleared to 0, a positive polarity is selected; when set to 1, a negative polarity is selected. ? by setting 1 to the corresponding bits among bits 2 to 7 of the pwm output control register 1, the pins are given the pwm output function to output the pwm. when clearing to 0, the pins become general- purpose ports (ports p0 0 Cp0 5 ). b7 b6 b5 b4 b3 b2 b1 b0 pwm output control register 2 (pn) [address 00d6 b after reset rw pwm output control register 2 0, 1 2 3 4 0 name functions da output polarity selection bit (pn3) 0 : positive polarity 1 : negative polarity pwm output polarity selection bit (pn4) nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. da general-purpose output bit (pn5) 0 : output low 1 : output high 5 to 7 0 0 0 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 : positive polarity 1 : negative polarity 16 ] r rw rw rw r fig. 2.10.7 pwm output control register 2 (address 00d6 16 )
7220 group users manual 2.11 crt display function 2.11 crt display function table 2.11.1 shows the outline the crt display function of the m37221m6-xxxsp/fp. m37220 m3-xxxsp/fp refer to chapter 4. m37220 m3-xxxsp/fp. the m37221m6-xxxsp/fp has the 24 characters 5 2 lines crt display circuit. crt display is controlled by the crt control register. up to 256 kinds of characters can be displayed, and colors can be specified for each character. up to 4 kinds of colors can be displayed on 1 screen. a combination of up to 7 colors can be obtained by using each output signal (r, g, and b). characters are displayed in a 12 5 16 dot structure to display smooth character patterns (refer to figure 2.11.1 ). how to display characters on the crt screen is described below. write the display character code in the display ram. specify the display color by the color register. a write the color register in which the display color is set in the display ram. ? specify the vertical position by the vertical position register. ? specify the character size by the character size register. ? specify the horizontal position by the horizontal position register. ? write the display control bit to the designated block display flag of the crt control register. when this is done, the crt starts according to the input of the v sync signal. the crt display circuit has an extended display mode. this mode allows multi-line (more than 3 lines) to be displayed on the screen by interrupting each time 1 line is displayed and rewriting data in the block which display is terminated by software. figure 2.11.2 shows the crt display circuit block diagram. figure 2.11.3 shows the crt control register. fig. 2.11.1 structure of crt display character table 2.11.1 outline of crt display function performance 24 characters 5 2 lines 12 dots 5 16 dots (refer to figure 2.11.1 ) 256 kinds 3 kinds 1 screen; 4 kinds, maximum 7 kinds a character possible (multi-line display) possible ( maximum 7 kinds) possible ( a character unit, 1 screen; 4 kinds, maximum 7 kinds) kinds of character kinds of character sizes parameter number of display character dot structure color display extension raster coloring character background coloring kind of colors coloring unit 12 dots 16 dots functional description
7220 group users manual functional description 2.11 crt display function fig. 2.11.2 crt display circuit block diagram crt control register (address 00ea 16 ) vertical position registers (addresses 00e1 16 , 00e2 16 ) character size register (address 00e4 16 ) horizontal position register (address 00e0 16 ) border selection register (address 00e5 16 ) display oscillation circuit osc1 osc2 display position control circuit h sync v sync display control circuit ram for display 10 bits 5 24 characters 5 2 lines color registers (addresses 00e6 16 to 00e9 16 ) crt port control register (address 00ec 16 ) data bus rom for display 12 bits 5 16 dots 5 256 characters shift register 12 bits shift register 12 bits output circuit r g b out1 out2
7220 group users manual 2.11 crt display function fig. 2.11.3 crt control register (address 00ea 16 ) b7 b6 b5 b4 b3 b2 b1 b0 crt control register (cc) [address 00ea 16 ] b name functions after reset r w crt control register 0 all-blocks display control bit (note) (cc0) 0 : all-blocks display off 1 : all-blocks display on 0 1 block 1 display control bit (cc1) 0 : block 1 display off 1 : block 1 display on 0 2 0 : block 2 display off 1 : block 2 display on 0 3 to 6 0 7p1 0 /out2 pin switch bit (cc7) 0 note: display is controlled by logical product (and) between the all-blocks display control bit and each block control bit. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. block 2 display control bit (cc2) rw rw rw r rw 0 : p1 0 1 : out2 functional description
7220 group user?s manual functional description 2.11 crt display function 2.11.1 display position the display positions of characters are specified in units c alled a block. there are 2 blocks, block 1 and block 2. up to 24 characters can be displayed in 1 block (re fer to 2.11.3 memory for display ). the display position of each block in both horizontal and ve rtical directions can be set by software. the horizontal direction is common to all blocks, and is sel ected from 64-step display positions in units of 4 t c (t c = oscillation cycle for display). the display position in the vertical direction is selected f rom 128-step display positions for each block in units of 4 scanning lines. the display position in the verti cal direction is determined by counting the horizontal sync signal (h sync ). at this time, it starts to count the rising edge (falling ed ge ] ) of h sync signal from after about 1 machine cycle of rising edge (falling edge ] ) of v sync signal. so interval from rising edge (falling edge ) of h sync signal needs enough time (2 machine cycles or more) for avoiding ji tter. ] : the polarity of h sync and v sync signals can select by the crt port control register (addres s 00ec 16 ). when clearing corresponding bits to 0, positive polarity i s selected, when setting to 1, negative polarity is selected. refer to 2.11.7 crt output pin control for detail. fig. 2.11.4 count method of synchronous signal when bits 0 and 1 of the crt port control register (address 00ec 16 ) are set to 1 (negative polarity) note 1: the vertical position is determined by counting falling edge of h sync signal after rising edge of v sync control signal in the microcomputer. 2: at f(x in ) = 8 mhz 3: do not generate falling edge of h sync signal near rising edge sync control signal in microcomputer to avoid jitter. 4: pulse width of v sync and of h sync signals needs 8 machine v sync signal input v sync control signal in microcomputer period of counting h sync signal h sync signal input 0.125 m s to 0.25 m s (see note 2) (see note 3) 1 234 5 not count 8 machine cycles or more (see note 4) 8 machine cycles or more (see note 4) cycles or more. of v ]
7220 group users manual 2.11 crt display function the block 2 is displayed after the display of block 1 is completed (refer to figure 2.11.5 (a) ). therefore, set vertical display start position of block 2 to be lower than the display end position of block 1. the block 2 cannot display when the display position of block 2 is overlapped with the display position of block 1 (refer to figure 2.11.5 (b) ) or is higher than the display position of block 1 (refer to figure 2.11.5 (c) ). same as above, at the multiline display, the next block 1 cannot be displayed until the display of block 2 is completed. therefore, set the display start position of the second and later block 1 to be lower than the display position of the last block 2 (refer to figure 2.11.5 (d) ). cv1 cv2 block 2 (hr) block 1 because the block 2 overlaps with the block 1, the block 2 cannot be displayed. (b) example when block 2 overlaps with block 1. cv1 cv2 (hr) block 1 (a) example when each block is separated. block 2 cv2 (c) example when the block 2 is higher than the block 1. cv1 cv2 (hr) because the block 2 is higher than the block 1, the block 2 cannot be displayed. block 1 cv1 (hr) because the block 1 overlaps with the last display of block 2, the block 1 cannot be displayed. block 1 (d) example when the block 1 overlaps with the last display of block 2 at the multiline display. block 1 (last display) block 2 (last display) (last displayed) fig. 2.11.5 display position functional description block 2
7220 group users manual functional description 2.11 crt display function fig. 2.11.6 vertical position register n (addresses 00e1 16 and 00e2 16 ) fig. 2.11.7 horizontal position register (address 00e0 16 ) the vertical position can specify 128-step positions (4 scanning lines per step) for each block by setting values 00 16 to 7f 16 to bits 0 to 6 of the vertical position registers (the blocks 1 and 2 are assigned to addresses to 00e1 16 , 00e2 16 respectively). figure 2.11.6 shows the vertical position registers. the horizontal direction is common to both blocks, and can specify 64-step display positions (4 t c per step, t c : oscillation cycle for display) by setting values 00 16 to 3f 16 to bits 0 to 5 of the horizontal position register (address 00e0 16 ). figure 2.11.7 shows the horizontal position register. b7 b6 b5 b4 b3 b2 b1 b0 vertical position register n (cv1,cv2) (n = 1 and 2) [addresses 00e1 16, 00e2 16 ] b name functions after reset r w vertical position register n 0 to 6 7 vertical display start positions 128 steps (00 16 to 7f 16 ) indeterminate 0 (cv1 : cv10 to cv16) nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. (cv2 : cv20 to cv26) rw r b7 b6 b5 b4 b3 b2 b1 b0 horizontal position register (hr) [address 00e0 16 ] b name functions after reset rw horizontal position register 0 to 5 6, 7 horizontal display start positions (hr0 to hr5) 64 steps (00 16 to 3f 16 ) 0 0 nothing is assigned. these bits are write disable bits. when thses bits are read out, the values are 0. rw r
7220 group user?s manual 2.11 crt display function fig. 2.11.8 character size register (address 00e4 16 ) note: the display start position in the horizontal direction is n ot affected by the character size. in other words, the horizontal display start position is common to al l blocks even when the character size varies with each block (refer to figure 2.11.9 ). fig. 2.11.9 display start position (horizontal direction) for each character size 2.11.2 character size the size of characters to be displayed can select from 3 siz es for each block. set a character size by the character size register (address 00e4 16 ). the character size in block 1 can be specified by bits 0 and 1 of the character size register; the character size in block 2 can be specified by bits 2 and 3. figure 2.1 1.8 shows the character size register. the character size can select three sizes: minimum size, medium size, and large size. each character size is determined with the number of scanning lines in the height (vertical) direction and the oscillation cycle for display (= t c ) in the width (horizontal) direction. the minimum size consists of [1 scanning line] 5 [1 t c ]; the medium size consists of [2 scanning lines] 5 [2 t c ] ; and the large size consists of [3 scanning lines] 5 [3 t c ]. table 2.11.2 shows the relationship between the set values in the character size register and the character sizes. table 2.11.2 relationship between set value in character siz e register and character sizes width (horizontal) direction t c : oscillation cycle for display 1 t c 2 t c 3 t c height (vertical) direction scanning lines 1 line 2 lines 3 lines set values in character size register csn1 0 0 1 1 csn0 0 1 0 1 minimum medium large character size this is not available. b7 b6 b5 b4 b3 b2 b1 b0 character size register (cs) [address 00e4 16 ] b name functions after reset r w character size register 0, 1 character size of block 1 selection bits (cs10, cs11) 00 : minimum size 01 : medium size 10 : large size 11 : do not set. indeterminate 2,3 4 to 7 0 character size of block 2 selection bits (cs20,cs21) 00 : minimum size 01 : medium size 10 : large size 11 : do not set. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. indeterminate rw rw r minimum size medium size large size display start position functional description
7220 group users manual functional description 2.11 crt display function 2.11.3 memory for display there are 2 types of display memory: crt display rom (addresses 10000 16 to 11fff 16 ) used to store (masked) character dot data and crt display ram (addresses 0600 16 to 06b7 16 ) used to specify the colors and characters to be displayed. each type of display memory is described below. (1) crt display rom (addresses 10000 16 to 11fff 16 ) crt display rom stores dot pattern data for characters to be displayed. when actually displaying characters stored in this rom, it is necessary to specify them by writing the character code inherent to each character (code determined based on the addresses in crt display rom) into crt display ram. crt display rom has a capacity of 8 k bytes. since 32 bytes are required for 1 character data, the rom can stores up to 256 kinds of characters. crt display rom is broadly divided into 2 areas. the [vertical 16 dots] 5 [horizontal (left side) 8 dots] data of display characters are stored in addresses 10000 16 to 107ff 16 and 11000 16 to 117ff 16 ; the [vertical 16 dots] 5 [horizontal (right side) 4 dots] data of display characters are stored in addresses 10800 16 to 10fff 16 , 11800 16 to 11fff 16 (refer to figure 2.11.10 ). note however that the high-order 4 bits of the data to be written to addresses 10800 16 to 10fff 16 and 11800 16 to 11fff 16 must be set to 1 (by writing data fx 16 ). fig. 2.11.10 example of display character data storing form 10xx0 16 +800 16 or 11xx0 16 +800 16 0 000000 0000000 0000010 0000101 0001000 0001000 0001000 0010000 0 1 01 1111 001 0100000 0100000 0100000 0000000 0000101 0000010 0 1111 000 0 000 0 000 0 000 0 000 0 000 0 000 0 100 0 100 0 100 0 010 0 010 0 010 0 000 0 000 0 000 10xxf 16 +800 16 or 11xxf 16 +800 16 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 b7 b0 b7 b0 b3 10xx0 16 or 11xx0 16 10xxf 16 or 11xxf 16 0 0000 0 0 0 0 0 1 1 1 0 0 0 0 0 0
7220 group user?s manual functional description 2.11 crt display function left side 8 dots 10000 16 to 1000f 16 10010 16 to 1001f 16 10020 16 to 1002f 16 10030 16 to 1003f 16 : 107e0 16 to 107ef 16 107f0 16 to 107ef 16 11000 16 to 1100f 16 11010 16 to 1101f 16 : 117d0 16 to 117df 16 117e0 16 to 117ef 16 117f0 16 to 117ef 16 right 4 side 8 dots 10800 16 to 1080f 16 10810 16 to 1081f 16 10820 16 to 1082f 16 10830 16 to 1083f 16 : 10fe0 16 to 10fef 16 10ff0 16 to 10fff 16 11800 16 to 1180f 16 11810 16 to 1181f 16 : 11fd0 16 to 11fdf 16 11fe0 16 to 11fef 16 11ff0 16 to 11fff 16 the character code used to specify a display character is de termined based on the address in the crt display rom in which that character data is stored. assume that 1 character data is stored in addresses 10xx0 16 to 10xxf 16 (xx denotes 00 16 to 7f 16 ) and 10yy0 16 to 10yyf 16 (yy denotes xx + 800 16 ), then the character code is xx 16 . in other words, a character code is constructed with the low -order second and third digits (hexadecimal notation) of the 5-digit address (10000 16 to 107ff 16 ) where that character data is stored. a character code is yy 16 in addresses 11000 16 to 11fff 16 . table 2.11.3 shows the character code table. table 2.11.3 character code table ( be omitted partly ) character data stored address character code 00 16 01 16 02 16 03 16 : 7e 16 7f 16 80 16 81 16 : fd 16 fe 16 ff 16
7220 group users manual functional description 2.11 crt display function not used display position (from left side) 1st character 2nd character 3rd character : 22nd character 23rd character 24th character 1st character 2nd character 3rd character : 22nd character 23rd character 24th character 0680 16 0681 16 0682 16 : 0695 16 0696 16 0697 16 0698 16 : 069f 16 06a0 16 06a1 16 06a2 16 : 06b5 16 06b6 16 06b7 16 (2) crt display ram (addresses 0600 16 to 06b7 16 ) crt display ram is assigned to addresses 0600 16 to 06b7 16 , and is divided into a display character code specification part and display color specification part for each block. table 2.11.4 shows the contents of crt display ram. for example, to display a character at the first character position (leftmost) in block 1, it is necessary to write the character code in address 0600 16 and the color register no. to the low-order 2 bits (bits 0 and 1) at address 0680 16 . the color register no. to be written here is one of the 4 color registers in which display color is set in advance. for details on color registers, refer to 2.11.4 color registers. table 2.11.4 contents of crt display ram block number block 1 block 2 character code specifying 0600 16 0601 16 0602 16 : 0615 16 0616 16 0617 16 0618 16 to 061f 16 0620 16 0621 16 0622 16 : 0635 16 0636 16 0637 16 color specifying
7220 group users manual functional description 2.11 crt display function fig. 2.11.11 structure of crt display ram figure 2.11.11 shows the structure of crt display ram. [color specification] 0 0 : specifying color register 0 0 1 : specifying color register 1 1 0 : specifying color register 2 1 1 : specifying color register 3 color register specification 0 1 block 1 [character specification] specify 256 characters (00 16 to ff 16 ) character code 70 block 2 [character specification] 1st character : 0620 16 24th character : 0637 16 1st character : 0680 16 24th character : 0697 16 1st character : 0600 16 24th character : 0617 16 70 [color specification] 1st character : 06a0 16 24th character : 06b7 16 0 1 to to to to specify 256 characters (00 16 to ff 16 ) character code 0 0 : specifying color register 0 0 1 : specifying color register 1 1 0 : specifying color register 2 1 1 : specifying color register 3 color register specification
7220 group users manual functional description 2.11 crt display function 2.11.4 color registers a display character color can be specified by setting a color to one of 4 color registers (co0 to co3: addresses 00e6 16 to 00e9 16 ) and then by specifying the color register with the crt display ram. there are 3 color outputs: r, g, and b. by a combination of these outputs, it is possible to set 2 3 C 1 (no output) = 7 colors. however, since color registers are only 4, up to 4 colors can be displayed at one time. r, g, and b outputs are set by bits 1 to 3 of the color register. bit 5 is used to specify either a character output or blank output. figure 2.11.12 shows the color register. either character output or blank output is selected as the out1 pin output. whether blank output or not is selected as the out2 pin output. fig. 2.11.12 color register n (addresses 00e6 16 to 00e9 16 ) b7 b6 b5 b4 b3 b2 b1 b0 color register n (co0 to co3) (n = 0 to 3) [addresses 00e6 16 to 00e9 16 ] b name functions after reset r w color register n 0 0 1 b signal output selection bit (con1) 0 : no character is output 1 : character is output 0 2 g signal output selection bit (con2) 0 : no character is output 1 : character is output 0 3 r signal output selection bit (con3) 0 : no character is output 1 : character is output 0 4 b signal output (background) selection bit (con4) 0 : no background color is output 1 : background color is output 0 5 out1 signal output control bit (con5) 0 : character is output 1 : blank is output 0 6 g signal output (background) selection bit (con6) 0 : no background color is output 1 : background color is output 0 7 r signal output (background) selection bit (con7) 0 : no background color is output 1 : background color is output 0 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. (see note 1) (see notes 1, 2) (see note 2) notes 1: when bit 5 = 0 and bit 4 = 1, there is output same as a character or border output from the out1 pin. do not set bit 5 = 0 and bit 4 = 0. 2: when only bit 7 = 1 and bit 5 = 0, there is output from the out2 pin. r rw rw rw rw rw rw rw
7220 group users manual 2.11 crt display function table 2.11.5 display example of character background coloring (when green is set for a character and blue is set for background color) border selection register color register con 7 con 6 con 5 con 4 con 3 con 2 con 1 md 0 g output b output out1 output character output out2 output 0 5 0 0 1 0 no output same output as character a green video signal and character color (green) are not mixed. no output (note 2) 0 0 5 0 0 1 0 no output same output as character a video signal and character color (green) are not mixed. blank output 1 green no output tv image of character background is not displayed. blank output green no output (note 2) 1 5 0 1 0 1 0 no output border output (black) video signal and character color (green) are not mixed. green no output (note 2) 010010 00 1 tv image of character background is not displayed. blank output green 01010 00 no output (note 2) background color blue 5 10 tv image of character background is not displayed. green 1 010 blank output 00 no output (note 2) black no output 11 green no output (note 2) 1 010 tv image of character background is not displayed. blank output 00 border output (black) background color C border blue notes 5 = 0 and con 4 = 1, there is output same as a character or border output from the out1 pin. do not set con 5 = 0 and con 4 = 0. 2 : 1 : when only con 7 = 1 and con 5 = 0, there is output from the out2 pin. 3 : 4 : 5 : 5 : 0 or 1 border output (black) 1 (note 1) 1 functional description when con the portion a in which character dots are displayed is not mixed with any tv video signal. the wavy-lined arrows in the table denote video signals. n : 0 to 3,
7220 group users manual functional description 2.11 crt display function fig. 2.11.13 generation timing of crt interrupt request fig. 2.11.14 display state of blocks and occurrence of crt interrupt request 2.11.5 multi-line display the m37221m6-xxxsp/fp can ordinarily display 2 lines on the crt screen by displaying 2 blocks at different vertical positions. in addition, it can display up to 16 lines by using a crt interrupt. a crt interrupt request occurs at which display of each block has been completed. in other words, character display of a certain block starts when a scanning line reaches the display position (specified by vertical position registers) for that block, and an interrupt occurs when the scanning line exceeds the block. for multi-line display, it is necessary to enable the crt interrupt (by clearing the interrupt disable flag to 0 and setting the crt interrupt enable bit = bit 4 at address 00fe 16 to 1). in a crt interrupt processing routine, the character data and vertical position of the block of which display has been completed (the display as crt interrupt cause is completed) is then replaced with the character data (contents of crt display ram) and display position (contents of vertical position register) for next display. notes 1: set the second and later block 1 display start positions of block 1 to be lower than display position of the last block 2. 2: the crt interrupt request does not occur at the end of display when the block is not displayed. in other words, if a block is set to off display with the display control bit of the crt control register (at address 00ea 16 ), a crt interrupt request does not occurs (refer to figure 2.11.14 ). crt interrupt request block 1 block 2 block 1 , block 2 , block 1 (on display) block 2 (on display) block 2 (off display) crt interrupt request on display (crt interrupt request occurs at the end of block display) off display (crt interrupt request does not occur at the end of block display) block 1 (off display)
7220 group users manual functional description 2.11 crt display function fig. 2.11.16 border selection register (address 00e5 16 ) 2.11.6 character border function an border of 1 clock (1 dot) equivalent size can be added to a display character in both horizontal and vertical directions. the border is output from pin out 1. in this case, set bit 5 of a color register to 0 (character is output). border can be specified each block by the border selection register (address 00e5 16 ). table 2.11.6 shows the relationship between the set values of the border selection register and the character border function. figure 2.11.16 shows the border selection register. fig. 2.11.15 border example table 2.11.6 relationship between set value of border selection register and character border function border selection register mdn0 functions example of output 0 1 ordinary border including character r, g, b output out1 output r, g, b output out1 output border dots character data dots b7 b6 b5 b4 b3 b2 b1 b0 border selection register (md) [address 00e5 16 ] b name functions after reset r w border selection register 0 block 1 out1 output border selection bit (md10) 0 : same output as character output 1 : border output indeterminate 1 2 block 1 out1 output border selection bit (md20) 0 : same output as character output 1 : border output 0 0 3 to 7 nothing is assigned. this bit is a write disable bits. when this bit is read out, the value is 0. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. indeterminate rw r rw r
7220 group user?s manual functional description 2.11 crt display function 2.11.7 crt output pin control crt display output pins r, g, b, and out1 are also used for ports p5 2 Cp5 5 respectively. when clearing the corresponding bits of the port p5 direction register (ad dress 00cb 16 ) to 0, the pins are set for crt output pins, when setting to 1, the pins are set for gener al-purpose port p5. pin put2 is also used for port p1 0 . when clearing bit 7 of the crt control register (address 0 0ea 16 ) to 0, the pin is set for port p1 0 , when setting to 1, the pin is set for pin out2. immediately after reset release, because the port p5 directi on register is reset, they become crt output pins r, g, b, and out. bits 0 to 4 of the crt port control register (address 00ec 16 ) can determine h sync and v sync input polarity and r, g, b, out1, and out2 output polarity. when clearing c orresponding bits to 0, positive polarity is selected, when setting to 1, negative polarity is selec ted. figure 2.11.17 shows the crt port control. fig. 2.11.17 crt port control register (address 00ec 16 ) b7 b6 b5 b4 b3 b2 b1 b0 crt port control register (crtp) [address 00ec 16 ] b name functions after reset r w crt port control register 0h sync input polarity switch bit (hsyc) 0 : positive polarity 1 : negative polarity 0 1 0 : positive polarity 1 : negative polarity 0 2 r, g, b output polarity switch bit (r/g/b) 0 : positive polarity 1 : negative polarity 0 3 out2 output polarity switch bit (out2) 0 : positive polarity 1 : negative polarity 0 4 out1 output polarity switch bit (out1) 0 : positive polarity 1 : negative polarity 0 5 r signal output switch bit (op5) 0 : r signal output 1 : mute signal output 0 6 g signal output switch bit (op6) 0 : g signal output 1 : mute signal output 0 7 b signal output switch bit (op7) 0 : b signal output 1 : mute signal output 0 v sync input polarity switch bit (vsyc) rw rw rw rw rw rw rw rw
7220 group users manual 2.11 crt display function 2.11.8 raster coloring function r, g, b, and out1 output can be switched to mute output. mute output can color all displaying area (raster) of screen. for example, the case that pin b is specified for mute signal output is shown in figure 2.11.18. when the mute signal is output from pin b, the background of the entire screen is colored blue. then, a character data is output from pin r, for example. when b and r signal outputs are set to character is output by the color register at the character i output, the output character is colored yellow (red mixed blue) regardless of the out1 signal output. when outputting the character o, the output character is colored only red that is not mixed blue by setting only r signal output to character is output. however, in this case, set pin out1 to blank is output. the tv image can be also erase by setting the all r, g, and b pins to mute output. the mute signal is output from pin out1 output, regardless of setting crt display ram for pin out1. whether ordinary video signal outputs or mute signal outputs from pins r, g, and b is controlled by bits 5 to 7 of the crt port control register (refer to figure 2.11.17 ). fig. 2.11.18 mute signal output example a red blue h sync r b out 1 signals across a-a' functional description a'
7220 group users manual functional description 2.11 crt display function 2.11.9 clock for display as a clock for display to be used for crt display, it is possible to select one of the following 4 types. l main clock supplied from the x in pin l main clock supplied from the x in pin divided by 1.5 l clock from the lc or rc supplied from the pins osc1 and osc2. l clock from the ceramic resonator or quartz-crystal oscillator supplied from the pins osc1 and osc2. this clock for display can be selected by the crt clock selection register (address 00ed 16 ). when selecting the main clock, set the oscillation frequency to 8 mhz. fig. 2.11.19 crt clock selection register b7 b6 b5 b4 b3 b2 b1 b0 crt clock selection register (ck) [address 00ed b name functions after reset r w crt clock selection register 0, 1 crt clock selection bits (ck0,ck1) 0 since the main clock is used as the clock for display, the oscillation frequency is limited. because of this, the character size in width (horizontal) direction is also limited. in this case, pins osc1 and osc2 are also used as input ports p3 3 and p3 4 respectively. the clock for display is supplied by connecting the following across the pins osc1 and osc2. ? a ceramic resonator only for crt display and a feedback resistor ? a quartz-crystal oscillator only for crt display and a feedback resistor (note) 2 to 7 0 0 0 0 0 0 0 b1 the clock for display is supplied by connecting rc or lc across the pins osc1 and osc2. functions 10 b0 crt oscillation frequency = f(x in ) crt oscillation frequency = f(x in )/1.5 note: it is necessary to connect other ceramic resonator or quartz-crystal oscillator across the pins x 0 0 1 1 1 1 fix these bits to 0. in and x out . 16 ] rw rw
7220 group users manual 2.12 rom correction function 2.12 rom correction function only the m37221m8-xxxsp and the m37221ma-xxxsp have this function. this can correct rom program data in rom. up to 2 addresses (2 blocks) can be corrected, a program for correction is stored in the rom correction memory in ram. the rom memory for correction is 32 bytes 5 2 blocks. block 1 : addresses 02c0 16 to 02df 16 block 2 : addresses 02e0 16 to 02ff 16 set an address of the rom data to be corrected into the rom correction address register. when the value of the counter matches the rom data address in the rom correction address, the main program branches to the correction program stored in the rom correction memory. to return from the correction program to the main program, the op code and operand of the jmp instruction (total of 3 bytes) are necessary at the end of the correction program. when the blocks 1 and 2 are used in series, the above instruction is not needed at the end of the block 1. the rom correction function is controlled by the rom correction enable register. notes 1 : specify the first address (op code address) of each instruction as the rom correction address. 2 : use the jmp instruction (total of 3 bytes) to return from the correction program to the main program. 3 : do not set the same address to rom correction addresses 1 and 2 (addresses to 0217 16 to 021a 16 ). fig. 2.12.1 rom correction address registers 0217 16 rom correction address 1 (high-order) 0218 16 rom correction address 1 (low-order) 0219 16 rom correction address 2 (high-order) 021a 16 rom correction address 2 (low-order) fig. 2.12.2 rom correction enable register b7 b6 b5 b4 b3 b2 b1 b0 rom correction enable register (rcr) [address 0212 16 ] b after reset rw rom correction enable register 0 block 1 enable bit (rcr0) name functions 0: disabled 1: enabled 1 block 2 enable bit (rcr1) 0: disabled 1: enabled 4 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 0 0 2, 3 fix these bits to 0. 0 00 rw rw r r functional description
7220 group users manual functional description 2.13 software runaway detect function fig. 2.13.1 sequence at detecting software runaway detection 2.13 software runaway detect function the m37221m6-xxxsp/fp has a function to decode undefined instructions to detect a software runaway. when an undefined op-code is input to the cpu as an instruction code during operation of the m37221m6- xxxsp/fp, the following processing is done. the cpu generates an undefined instruction decoding signal. the device is internally reset because of occurrence of the undefined instruction decoding signal. a as a result of internal reset, the same reset processing as in the case of ordinary reset operation is done, and the program restarts from the reset vector. note, however, that the software runaway detecting function cannot be invalid. ad h , ad l 01,sC2 01,sC1 pc h pc l ps ad h ad l pc ? ? : undefined instruction decode ? undefined instruction decoding signal occurs. internal reset signal occurs. f sync address data reset sequence 01,s fffe 16 ffff 16 : invalid : program counter s : stack pointer pc ad l , ad h : jump destination address of reset
7220 group users manual 2.14 low-power dissipation mode 2.14 low-power dissipation mode the m37221m6-xxxsp/fp has 2 low-power dissipation modes: the stop mode and the wait mode. 2.14.1 stop mode the m37221m6-xxxsp/fp allows the oscillation of x in to be stopped with keeping all states of registers except timers 3 and 4, input/output ports, and internal ram. therefore, the m37221m6-xxxsp/fp can be restarted with the same state where oscillation was stopped, and as a result, the power dissipation can be greatly reduced. to stop oscillating in such a way, execute the stp instruction. the stop mode is set by executing the stp instruction. in this mode, the address to fetch the instruction next to the stp instruction is output to the address bus, and the oscillation stops with high state of the internal clock f . at this time, the timer 3 overflow signal is further connected to timer 4. value ff 16 is automatically set to timer 3; value 07 16 is automatically set to timer 4. immediately before executing the stp instruction, process the following sequence: store registers (accumulator, index registers, etc.) in the cpu to internal ram. disable timers 3 and 4 interrupts (tm3e = tm4e = 0). a clear timers 3 and 4 count stop bits to 0 (t34m2 = t34m3 = 0). ? when an interrupt is used for return from the stop mode, enable that interrupt (by clearing the interrupt disable flag to 0 and setting the interrupt enable bit to 1). ? set bit 0 of the timer 34 mode register (address 00f5 16 ) to 0 (tm34m0=0) to select f(x in )/16 as the timer 3 count source. oscillation is restarted (return from the stop mode) by accepting reset input or interrupt request of int1, int2 or int3. when the interrupt request is accepted, the interrupt processing routine is executed. note, however, that the internal clock f is not supplied to the cpu until timer 4 overflows after the interrupt request is accepted. this is because a finite time is required for stabilizing of oscillation when an external quartz-crystal oscillator, etc. is used. when the internal clock f is supplied to the cpu, the cpu executes the interrupt routine. at this time, the address for the first byte of the instruction next to the stp instruction is pushed to the stack as a return address. also note that the timers 3 and 4 interrupt request bits are remained setting to 1. therefore, clear each bit to 0 in the interrupt routine. enable one of the int1, int2 and int3 interrupts to use interrupts for restarting oscillation before the executing stp instruction (described in ? above). table 2.14.1 state in stop mode state in stop mode item oscillation cpu internal clock f i/o ports timer, crt display functions stops stops stops at high level state where stp instruction is executed is held. stops functional description
7220 group users manual functional description 2.14 low-power dissipation mode fig. 2.14.1 oscillation stabilizing time at return by reset input fig. 2.14.2 execution sequence example at return by occurrence of int0 interrupt request timer 4 counter lwhen returning from stop mode by using int1 interrupt (rising edge selected) x in (system clock) ff 16 int1 pin peripheral device cpu stop mode timer 3 counter 07 16 2048 counts ?int1 interrupt signal is input (int1 interrupt request occurs) ?oscillation starts ?timer 3 count starts ?execute stp instruction stopping operating stopping operating oscillation stabilizing time (approximately 32768 cycles) x in ; high x cin ; in high-impedance state oper- ating int1 interrupt request bit ?2048 counts down by timer 3 ?supplying internal clock f to cpu is started ?int1 interrupt request is accepted oper- ating reset x in v cc execute stp instruction returned by reset input oscillation stabilizing time stop mode 2 m s or more time to hold internal reset state = approximately 32768 cycles of x in input (note)
7220 group users manual 2.14 low-power dissipation mode 2.14.2 wait mode the wait mode is set by executing the wit instruction. in the wait mode, only the internal clock f stops with supplying f(x in ) continuously. in this case, there is no need to create a wait time by timers as in the case of return from the stop mode, and operation is restarted immediately after return from the wait state. when reset input or interrupt is accepted, supply of the internal clock f is immediately started, and the device is returned from the wait state. because the clock f(x in ) is continuously supplied in the wait state, return by an internal interrupt as a timer, etc. can also be used. table 2.14.2 state in wait mode the following 2 kinds of interrupts can be used to return from the stop mode to the ordinary mode. int1 interrupt int2 interrupt a int3 interrupt figure 2.14.4 shows a transitions of low-power dissipation mode. table 2.14.3 invalid interrupts in the wait mode fig. 2.14.3 reset input time 2.14.3 interrupts in low-power dissipation mode the following 4 kinds of interrupts are invalid in the wait mode. therefore, 4 interrupts below cannot be used to return from the wait mode to the ordinary mode. oscillation cpu internal clock f i/o ports timer, crt display functions operating stop stop at high level state where wit instruction is executed is held. operating state in wait mode item interrupt source reason condition v sync interrupt crt interrupt timer 2 interrupt timer 3 interrupt count source is input from pin p2 4 /tim2. count source is input from pin p2 3 /tim3. the interrupt request bit cannot be set. the count source cannot be supplied. the count source cannot be supplied. reset x in v cc execute wit instruction returned by reset input wait mode 2 m s or more oscillation stabilizing time (note) time to hold internal reset state = approximately 32768 cycles of x in input functional description
7220 group users manual functional description 2.14 low-power dissipation mode reset ordinary mode 8 mhz oscillating f = 4 mhz wait mode 8 mhz oscillating f is stopped timer operating stop mode 8 mhz stopped f is stopped (note 1) (note 2) * at f(x in ) = 8 mh z notes 1: the following interrupts are invalid in the wait mode. (1) v sync interrupt (2) crt interrupt (3) timer 2 interrupt that count source is supplied from pin p2 4 /tim2. (4) timer 3 interrupt that count source is supplied from pin p2 3 /tim3. fig. 2.14.4 state transitions of low-power dissipation mode
7220 group users manual 2.15 reset fig. 2.15.1 timing diagram at reset 2.15 reset to reset the microcomputer, applied low level to pin reset for 2 s or more. reset is released when high level is applied to pin reset, and the program starts from the address indicated with the reset vector table. 2.15.1 reset operation if pin reset is returned to an high level after being held low for 2 s or more when the power source voltage is within the recommended range (4.5 v to 5.5 v), timers 3 and 4 are connected by hardware with internally reset state (internal timing signal f is not supplied). at this time, ff 16 is set to timer 3, and 07 16 is set to timer 4. timer 3 counts down f(x in )/16 as its count source; timer 4 counts down the timer 3 overflow signal (even when the device is in internally reset state, f(x in ) is continuously supplied to timer 3). the internal reset is released by timer 4 overflow, and the program is started from an address determined with the contents of address ffff 16 (as high-order address) and contents of address fffe 16 (as low-order address). figure 2.15.1 shows this sequence. ad h , ad l 01,sC2 01,sC1 pc h pc l ps ad h ad l ? ? 01,s fffe 16 ffff 16 ? ? f sync address data reset internal reset x in notes 1: f(x in ) and f( f ) are in the relation : f(x in ) = 2?f( f ). 2: a question mark (?) indicates an undefined state that depends on the previous state. 3: immediately after a reset, timer 3 and timer 4 are connected by hardware. at this time, ff 16 is set in timer 3 and 07 16 is set to timer 4. timer 3 counts down with f(x in )/16, and reset state is released by the timer 4 overflow signal. 32,768 counts of f(x in ) by timers 3 and 4 functional description
7220 group users manual functional description 2.15 reset 2.15.2 internal state immediately after reset figures 2.15.2 to 2.15.4 show the internal state immediately after reset. fig. 2.15.2 internal state immediately after reset (1) n sfr area (addresses c0 16 to df 16 ) d0 16 d1 16 d2 16 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 c0 16 c1 16 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c9 16 cb 16 cc 16 cd 16 ce 16 cf 16 ca 16 address port p5 (p5) port p5 direction register (d5) port p3 output mode control register (p3s) da-h register (da-h) da-l register (da-l) pwm0 register (pwm0) port p1 (p1) port p1 direction register (d1) port p3 (p3) port p3 direction register (d3) port p2 (p2) port p2 direction register (d2) register port p0 (p0) port p0 direction register (d0) pwm1 register (pwm1) pwm2 register (pwm2) pwm3 register (pwm3) pwm4 register (pwm4) pwm output control register 1 (pw) pwm output control register 2 (pn) serial i/o mode register (sm) serial i/o register (sio) i c data shift register (s0) 2 i c address register (s0d) 2 i c status register (s1) 2 i c control register (s1d) 2 i c clock control register (s2) 2 : indeterminate immediately after reset : 0 immediately after reset 0 1 ? < state immediately after reset > : 1 immediately after reset ? 00 16 b7 b0 ? 00 16 ? 00 16 ? ? ? ? ? 0 0 0 ? ? 0 0 ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? ? ? ? ? 00 16 ? ? ? ? 00 16 00 16 00 16 0 0 00 0 1? 0 state immediately after reset 00 16 00 16 00 16 00 16 00 16 00 16 00 16
7220 group users manual 2.15 reset f0 16 f1 16 f2 16 f3 16 f4 16 f5 16 f6 16 f7 16 f8 16 f9 16 fa 16 fb 16 fc 16 fd 16 fe 16 ff 16 e0 16 e1 16 e2 16 e3 16 e4 16 e5 16 e6 16 e7 16 e8 16 e9 16 eb 16 ec 16 ed 16 ee 16 ef 16 ea 16 address crt control register (cc) crt port control register (crtp) a-d control register 1 (ad1) a-d control register 2 (ad2) timer 1 (tm1) vertical position register 2 (cv2) color register 0 (co0) color register 1 (co1) character size register (cs) border selection register (md) register horizontal position register (hr) vertical position register 1 (cv1) timer 2 (tm2) timer 3 (tm3) timer 4 (tm4) timer 12 mode register (t12m) timer 34 mode register (t34m) pwm5 register (pwm5) interrupt input polarity register (re) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) color register 2 (co2) color register 3 (co3) crt clock selection register (ck) cpu mode register (cpum) n sfr area (addresses e0 16 to ff 16 ) ? b7 b0 0 ?????? ? 0 ?????? ? ???? 0000 ?? 00000 0 ? 00 16 ? 00 00 0 0 0 ? ? ? 00 00 0? 0 1 ? 0 00 16 ? 11 1 00 state immediately after reset : 0 immediately after reset 0 1 ? < state immediately after reset > : 1 immediately after reset : indeterminate immediately after reset ff 16 07 16 ff 16 07 16 ff 16 07 16 ff 16 07 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 fig. 2.15.3 internal state immediately after reset (2) functional description
7220 group users manual functional description 2.15 reset fig. 2.15.4 internal state immediately after reset (3) (only m37221m8-xxxsp and m37221ma-xxxsp) 217 16 218 16 219 16 21a 16 21b 16 address register rom correction address 1 (high-order) n 2 page register area (addresses 217 16 to 21b 16 ) rom correction address 1 (low-order) rom correction address 2 (high-order) rom correction address 2 (low-order) rom correction enable register (rcr) b7 b0 ? ? ? ? state immediately after reset : 0 immediately after reset 0 1 ? < state immediately after reset > : 1 immediately after reset : indeterminate immediately after reset 00 16
7220 group users manual 2.15 reset 2.15.3 notes for poweron reset when poweron reset, set the external reset circuit so that the reset input voltage must be kept 0.6 v or less until the power source voltage reaches 4.5 v after the power is turned on. set the external reset circuit so that the reset input voltage must be kept 0.6 v or less when the power source voltage falls 4.5 v after the power is turned off. figures 2.15.5 to 2.15.7 show examples of external reset circuit. fig. 2.15.5 voltage at poweron reset fig. 2.15.7 example of reset circuit (2) fig. 2.15.6 example of reset circuit (1) m37221m6- xxxsp/fp v ss reset v cc reset v cc m37221m6- xxxsp/fp v ss v cc m37221m6- xxxsp/fp reset poweron 0 v 0.6 v 0 v 4.5 v power source voltage reset input voltage functional description
7220 group users manual functional description 2.16 clock generating circuit fig. 2.16.1 clock generating circuit block diagram 2.16 clock generating circuit oscillation circuit consists of an oscillation gate which operates as an amplifier to provide the gain required for oscillation and an oscillating control flip-flop to control this. because of that, it is possible to start and stop oscillating as required. for details concerning start and stop of oscillation, refer to 2.14 low-power dissipation mode. figure 2.16.1 shows the clock generating circuit block diagram. interrupt request interrupt disable flag i reset sq r stp instruction sq r wit instruction s q r stp instruction reset internal clock f 1/2 1/8 timer 3 timer 4 x out x in t34m0 t34m2 selection gate : connected to black side at reset. . t34m : timer 34 mode register
7220 group users manual 2.17 oscillation circuit fig. 2.17.3 clock oscillation circuit for crt display 2.17 oscillation circuit the m37221m6-xxxsp/fp has a internal oscillation circuits used to obtain the clocks required for operation. ordinarily, the frequency on clock input pin x in divided by 2 is the internal clock (internal timing output) f . a quartz-crystal oscillator or ceramic resonator can be connected externally to these circuits. (1) oscillation circuit using a quartz-crystal oscillator or ceramic resonator figure 2.17.1 shows the circuit example using a quartz-crystal oscillator or a ceramic resonator. as shown in the diagram, oscillation circuit can be constructed by connecting a ceramic resonator (a quartz-crystal oscillator) between pins x in and x out . in this case, set the circuit constants for c in and c out to the values recommended by the resonator manufacturer. (2) external clock oscillation circuit supplying an external clock is possible, figure 2.17.2 shows the circuit example. fig. 2.17.1 clock oscillation circuit using a ceramic resonator the m37221m6-xxxsp/fp has a crt display clock oscillation circuit, so that display clock can be obtained simply by connecting a inductor and capacitor between pins osc1 and osc2. figure 2.17.3 shows the circuit example. refer to 2.11.9 clock for display. fig. 2.17.2 external clock input circuit example 19 20 v cc v ss external oscillation circuit open x in x out m37221m6-xxxsp/fp in the stop mode, keep the x in pin input signal at an h level. note: c in c out 19 20 x in x out m37221m6-xxxsp/fp c1 24 osc1 m37221m6-xxxsp/fp c2 23 osc2 l functional description
7220 group users manual electrical characteristics 3.1 electrical characteristics 3.1 electrical characteristics absolute maximum ratings notes 1: the total current that flows out of the ic must be 20 ma (max.). 2: the total input current to ic (i ol1 + i ol2 + i ol3 ) must be 30 ma or less. 3: the total average input current for ports p2 4 Cp2 7 to ic must be 20 ma or less. symbol v cc v i v i v o v o i oh i ol1 i ol2 i ol3 i ol4 p d t opr t stg parameter power source voltage v cc input voltage cnv ss input voltage p0 0 Cp0 7 ,p1 0 Cp1 7 , p2 0 C p2 7 , p3 0 Cp3 4 , osc1, x in , h sync , v sync , reset output voltage p0 6 , p0 7 , p1 0 Cp1 7 , p2 0 C p2 7 , p3 0 Cp3 2 , r, g, b, out1, d-a, x out , osc2 output voltage p0 0 Cp0 5 circuit current r, g, b, out1, p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , d-a circuit current r, g, b, out1, p0 6 , p0 7 , p1 0 , p1 5 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 2 , d-a circuit current p1 1 Cp1 4 circuit current p0 0 Cp0 5 circuit current p2 4 Cp2 7 power dissipation operating temperature storage temperature conditions all voltages are based on v ss . output transistors are cut off. t a = 25 c ratings C0.3 to 6 C0.3 to 6 C0.3 to v cc + 0.3 C0.3 to v cc + 0.3 C0.3 to 13 0 to 1 (note 1) 0 to 2 (note 2) 0 to 6 (note 2) 0 to 1 (note 2) 0 to 10 (note 3) 550 C10 to 70 C40 to 125 unit v v v v v ma ma ma ma ma mw c c
7220 group users manual electrical characteristics 3.1 electrical characteristics recommended operating conditions (t a = C10 c to 70 c, v cc = 5 v 10 %, unless otherwise noted) notes 1: the total current that flows out of the ic must be 20 ma (max.). 2: the total input current to ic (i ol1 + i ol2 + i ol3 ) must be 30 ma or less. 3: the total average input current for ports p2 4 Cp2 7 to ic must be 20 ma or less. 4: connect 0.1 f or more capacitor externally across the power source pins v cc Cv ss so as to reduce power source noise. also connect 0.1 f or more capacitor externally across the pins v cc Ccnv ss . 5: use a quartz-crystal oscillator or a ceramic resonator for the cpu oscillation circuit. min. 4.5 0 0.8v cc 0.7v cc 0 0 0 7.9 5.0 typ. 5.0 0 8.0 max. 5.5 0 v cc v cc 0.4v cc 0.3v cc 0.2v cc 1 2 6 1 10 8.1 8.0 100 1 400 v v v v v v v ma ma ma ma ma mhz mhz khz mhz khz unit parameter symbol v cc v ss v ih1 v ih2 v il1 v il2 v il3 i oh i ol1 i ol2 i ol3 i ol4 f(x in ) f crt f hs1 f hs2 f hs3 power source voltage (note 4), during cpu, crt operation power source voltage high input voltage p0 0 Cp0 7 ,p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 4 , s in , s clk , h sync , v sync , reset, x in , osc1, tim2, tim3, int1, int2, int3 high input voltage scl1, scl2, sda1, sda2 (when using i 2 c-bus) low input voltage p0 0 Cp0 7 ,p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 4 low input voltage scl1, scl2, sda1, sda2 (when using i 2 c-bus) low input voltage h sync , v sync , reset, tim2, tim3, int1, int2, int3, x in , osc1, s in , s clk high average output current (note 1) r, g, b, out1, d-a, p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 low average output current (note 2) r, g, b, out1, d-a, p0 6 , p0 7 , p1 0 , p1 5 Cp1 7 , p2 0 Cp2 7 , p3 0 C p3 2 low average output current (note 2) p1 1 Cp1 4 low average output current (note 2) p0 0 Cp0 5 low average output current (note 3) p2 4 Cp2 7 oscillation frequency (for cpu operation) (note 5) x in oscillation frequency (for crt display) (note 5) osc1 input frequency tim2, tim3 input frequency s clk input frequency scl1, scl2
7220 group users manual electrical characteristics 3.1 electrical characteristics v cc = 5.5 v, f(x in ) = 8 mhz v cc = 5.5 v, f(x in ) = 0 v cc = 4.5 v i oh = C0.5 ma v cc = 4.5 v i ol = 0.5 ma v cc = 4.5 v i ol = 3 ma i ol = 6 ma v cc = 4.5 v i ol = 10.0 ma v cc = 5.0 v v cc = 5.0 v v cc = 5.5 v v i = 5.5 v v cc = 5.5 v v i = 0 v v cc = 5.5 v v o = 12 v v cc = 4.5 v power source current high output voltage r, g, b, out1, d-a, p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 low output voltage r, g, b, out1, d-a, p0 0 Cp0 7 , p1 0 , p1 5 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 2 low output voltage p1 1 Cp1 4 low output voltage p2 4 Cp2 7 hysteresis reset hysteresis (note) h sync , v sync , tim2, tim3, int1, int2, int3, scl1, scl2, sda1, sda2, s in , s clk high input leak current reset, p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 4 , h sync , v sync low input leak current reset, p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 4 , h sync , v sync high output leak current p0 0 Cp0 5 i 2 c-busbus switch connection resistor (between scl1 and scl2, sda1 and sda2) electric characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = C10 c to 70 c, unless otherwise noted) note: p0 6 , p0 7 , p1 5 , p2 3 and p2 4 have the hysteresis when these pins are used as interrupt input pins or timer input pins. p2 0 Cp2 2 have the hysteresis when these pins are used as serial i/o pins. p1 1 Cp1 4 have the hysteresis when these pins are used as multi-master i 2 c-bus interface pins. symbol i cc v oh v ol v t+ Cv tC i izh i izl i ozh r bs system operation stop mode parameter test conditions crt off crt on max. 40 60 300 0.4 0.4 0.6 3.0 0.7 1.3 5 5 10 130 min. 2.4 typ. 20 30 0.5 0.5 limits ma a v v v a a a w unit
7220 group users manual 3.1 electrical characteristics typ. max. 300 0.9 300 1.3 0.6 1.3 20+0.1c b 0 0.6 20+0.1c b 100 0.6 0.6 a-d comparator characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = C10 c to 70 c, unless otherwise noted) note: when v cc = 5 v, 1 lsb = 5/64 v. multi-master i 2 c-bus bus line characteristics note: c b = total capacitance of 1 bus line fig. 3.1.1 definition diagram of timing on multi-master i 2 c-bus limits unit bits lsb typ. 1 max. 6 2 min. 0 parameter symbol test conditions resolution absolute accuracy standard clod mode high-speed clock mode unit min. max. s s s ns s s ns ns s s 4.7 4.0 4.7 0 4.0 250 4.7 4.0 1000 300 parameter symbol t buf t hd:sta t low t r t hd:dat t high t f t su:dat t su:sta t su:sto bus free time hold time for start condition low period of scl clock rising time of both scl and sda signals data hold time high period of scl clock falling time of both scl and sda signals data set-up time set-up time for repeated start condition set-up time for stop condition sda scl p t buf s t hd : sta t low t r t hd : dat t high t f t su : dat t su : sta sr p t su : sto t hd : sta s sr p : start condition : restart condition : stop condition electrical characteristics
7220 group user?s manual electrical characteristics 3.1 electrical characteristics 3.2 standar d c haracteristics the data described in this section are characteristic exampl es. refer to 3.1 electrical characteristics for rated values. 3.2 standard characteristics 100.00 0.000 0.000 low level output voltage v ol [v] low level output current i ol [ma] v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 1. ports p0 0 Cp0 5 and p3 2 (a) i ol Cv ol characteristics 20.00 40.00 60.00 80.00 100.00 0.000 0.000 low level output voltage v ol [v] high level output current i oh [ma] v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 2. ports p 0 6 and p0 7 (a) i oh Cv ol characteristics 20.00 40.00 60.00 80.00
7220 group users manual 3.1 electrical characteristics 3.2 standard characteristics 100.00 0.000 0.000 v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 3. ports p1 0 , p1 5 Cp1 7 , p2 0 Cp2 3 , p3 0, p3 1 and d-a (a) i ol Cv ol characteristics 20.00 40.00 60.00 80.00 C 100.00 0.000 0.000 high level output voltage v oh [v] high level output current i oh [ma] v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 (b) i ohC v oh characteristics 20.00 40.00 60.00 80.00 low level output voltage v ol [v] low level output current i ol [ma] electrical characteristics C C C C C CC C C
7220 group users manual electrical characteristics 3.1 electrical characteristics 3.2 standard characteristics 100.00 0.000 0.000 low level output voltage v ol [v] low level output current i ol [ma] v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 4. ports p1 1 Cp1 4 (a) i olC v ol characteristics 20.00 40.00 60.00 80.00 C 100.00 0.000 0.000 high level output voltage v oh [v] high level output current i oh [ma] v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 (b) i oh Cv oh characteristics 20.00 40.00 60.00 80.00 C C C C C CCCC
7220 group users manual electrical characteristics 3.1 electrical characteristics 3.2 standard characteristics 100.00 0.000 0.000 low level output voltage v ol [v] low level output current i ol [ma] v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 5. ports p2 4 Cp2 7 (a) i olC v ol characteristics 20.00 40.00 60.00 80.00 C 100.00 0.000 0.000 high level output voltage v oh [v] high level output current i oh [ma] v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 (b) i oh Cv oh characteristics 20.00 40.00 60.00 80.00 C C C C C C C C C
7220 group users manual electrical characteristics 3.1 electrical characteristics 3.2 standard characteristics 100.00 0.000 0.000 low level output voltage v ol [v] low level output current i ol [ma] v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 6. ports p5 2 Cp5 5 (a) i olC v ol characteristics 20.00 40.00 60.00 80.00 C 100.00 0.000 0.000 high level output voltage v oh [v] high level output current i oh [ma] v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 (b) i oh Cv oh characteristics 20.00 40.00 60.00 80.00 C C C C CC C CC
7220 m3-xxxsp/fp 4.1 performance overview 4.2 pin configuration 4.3 pin description 4.4 functional block diagram 4.5 functional description 4.6 electrical characteristics 4.7 standard characteristics
7220 m3-xxxsp/fp 4.1 performance overview 7220 group users manual 4-2 71 0.5 s (the minimum instruction execution time, at 8 mhz oscillation frequency) 8 mhz (maximum) 12 k bytes 256 bytes 4 k bytes 80 bytes 8-bit 5 1 (n-channel open-drain output structure, can be used as pwm output pins, int input pins, a-d input pin) 8-bit 5 1 (cmos input/output structure, can be used as a-d input pins, int input pin) 2-bit 5 1 (cmos input/output or n-channel open-drain output structure, can be used as serial i/o pins) 6-bit 5 1 (cmos input/output structure, can be used as serial input pin, external clock input pins) 2-bit 5 1 (cmos input/output or n-channel open-drain output structure, can be used as d-a conversion output pins, a-d input pins) 1-bit 5 1 (n-channel open-drain output structure) 2-bit 5 1 (can be used as crt display clock i/o pins) 4-bit 5 1 (cmos output structure, can be used as crt output pins) 8-bit 5 1 6 channels (6-bit resolution) 2 (6-bit resolution) 14-bit 5 1, 8-bit 5 6 8-bit timer 5 4 96 levels (maximum) external interrupt 5 3, internal timer interrupt 5 4, serial i/o interrupt 5 1, crt interrupt 5 1, f(x in )/4096 interrupt 5 1, v sync interrupt 5 1, brk interrupt 5 1 2 built-in circuits (externally connected a ceramic resonator or a quartz-crystal oscillator) 5 v 10 % number of basic instructions instruction execution time clock frequency memory size input/output ports serial i/o a-d comparator d-a converter pwm output circuit timers subroutine nesting interrupt clock generating circuit power source voltage 4.1 performance overview this chapter is described about m37220 m3-xxxsp/fp. m37220 m3-xxxsp/fp has the common functions with m37221m6-xxxsp/fp except for part of functions. this chapter explains the differences between m37220 m3-xxxsp/fp and m37221m6-xxxsp/fp. therefore, refer to the corresponding descriptions of m37221m6-xxxsp/fp about the common functions. the 8-bit microcomputer m37220 m3-xxxsp/fp has many additional functions for tuning system for tv: table 4.1.1 performance overview (1) parameter rom ram crt rom crt ram p0 0 Cp0 7 p1 0 Cp1 7 p2 0 , p2 1 p2 2 Cp2 7 p3 0 , p3 1 p3 2 p3 3 , p3 4 p5 2 Cp5 5 i/o i/o i/o i/o i/o i/o input output performance
7220 m3-xxxsp/fp 4.1 performance overview 4-3 7220 group users manual table 4.1.2 performance overview (2) power dissipation 12v withstand ports led drive ports operating temperature range device structure package crt display function performance parameter crt on crt off in stop mode 165 mw typ. (at oscillation frequency f(x in ) = 8 mhz, f crt = 8 mhz) 110 mw typ. (at oscillation frequency f(x in ) = 8 mhz) 1.65 mw (maximum) 6 4 C10 c to 70 c cmos silicon gate process 42-pin shrink plastic molded dip 42-pin shrink plastic molded sop 20 characters 5 2 lines (maximum 16 lines by software) 12 5 16 dots 128 kinds 3 kinds maximum 7 kinds (r, g, b); can be specified by the character 64 levels (horizontal) 5 128 levels (vertical) m37220 m3-xxxsp m37220 m3-xxxfp number of display characters dot structure kinds of characters kinds of character sizes kinds of character colors display position (horizontal, vertical)
7220 m3-xxxsp/fp 4.2 pin configuration 7220 group users manual 4-4 4.2 pin configuration the pin configurations are shown in figures 4.2.1 and 4.2.2. fig. 4.2.1 pin configuration (top view) (1) h sync v sync p0 0 /pwm0 p0 2 /pwm2 p0 1 /pwm1 p0 3 /pwm3 p0 4 /pwm4 p0 5 /pwm5 p0 6 /int2/a-d4 p0 7 /int1 p2 3 /tim3 p2 4 /tim2 p2 5 p2 6 p3 2 p2 7 d-a cnv ss x out v ss p3 1 /a-d6/da2 p1 0 p2 1 /s out p2 2 /s in p1 2 p1 1 p1 3 p1 4 p1 5 /a-d1/int3 p1 6 /a-d2 p1 7 /a-d3 osc1/p3 3 reset osc2/p3 4 v cc p3 0 /a-d5/da1 x in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 package type : 42p4b p5 2 /r p5 4 /b p5 3 /g p5 5 /out p2 0 /s clk 42 41 40 39 38 37 m37220 m3-xxxsp
7220 m3-xxxsp/fp 4.2 pin configuration 4-5 7220 group users manual fig. 4.2.2 pin configuration (top view) (2) h sync v sync p0 0 /pwm0 p0 2 /pwm2 p0 1 /pwm1 p0 3 /pwm3 p0 4 /pwm4 p0 5 /pwm5 p0 6 /int2/a-d4 p0 7 /int1 p2 3 /tim3 p2 4 /tim2 p2 5 p2 6 p3 2 p2 7 d-a cnv ss x out v ss p3 1 /a-d6/da2 p1 0 p2 1 /s out p2 2 /s in p1 2 p1 1 p1 3 p1 4 p1 5 /a-d1/int3 p1 6 /a-d2 p1 7 /a-d3 osc1/p3 3 reset osc2/p3 4 v cc p3 0 /a-d5/da1 x in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 package type : 42p2r-a p5 2 /r p5 4 /b p5 3 /g p5 5 /out p2 0 /s clk 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 42 41 40 39 38 37 m37220 m3-xxxfp
7220 m3-xxxsp/fp 4.3 pin description 7220 group users manual 4-6 4.3 pin description the pin description of m37220 m3-xxxsp/fp is shown in table 4.3.1. table 4.3.1 pin description (1) power source cnv ss reset input clock input clock output i/o port p0 pwm output external interrupt input analog input i/o port p1 analog input external interrupt input v cc , v ss cnv ss reset x in x out p0 0 pwm0C p0 5 / pwm5, p0 6 /int2/ a-d4 , p0 7 /int1 p1 1 Cp1 4 , p1 5 /a-d1/ int3, p1 6 /a-d2, p1 7 /a-d3 input input output i/o output input input i/o input input pin name input/ output functions apply voltage of 5 v 10 % (typical) to v cc , and 0 v to v ss . this is connected to v ss . to enter the reset state, the reset input pin must be kept at a l for 2 s or more (under normal v cc conditions). if more time is needed for the quartz-crystal oscillator to stabilize, this l condition should be maintained for the required time. this chip has an internal clock generating circuit. to control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins x in and x out . if an external clock is used, the clock source should be connected to the x in pin and the x out pin should be left open. port p0 is an 8-bit i/o port with direction register allowing each i/o bit to be individually programmed as input or output. at reset, this port is set to input mode. the output structure is n-channel open-drain output. the note out of this table gives a full of port p0 function. pins p0 0 Cp0 5 are also used as pwm output pins pwm0Cpwm5 respectively. the output structure is n-channel open-drain output. pins p0 6 , p0 7 are also used as external interrupt input pins int2, int1 respectively. p0 6 pin is also used as analog input pin a-d4. port p1 is an 8-bit i/o port and has basically the same functions as port p0. the output structure is cmos output. pins p1 5 Cp1 7 are also used as analog input pins a-d1 to a-d3 respectively. p1 5 pin is also used as external interrupt input pin int3.
7220 m3-xxxsp/fp 4.3 pin description 4-7 7220 group users manual port p2 is an 8-bit i/o port and has basically the same functions as port p0. the output structure is cmos output. pins p2 3 , p2 4 are also used as external clock input pins tim3, tim2 respectively. p2 0 pin is also used as serial i/o synchronous clock input/output pin s clk . the output structure is n-channel open-drain output. pins p2 1 , p2 2 are also used as serial i/o data input/output pins s out , s in respectively. the output structure is n-channel open-drain output. ports p3 0 Cp3 2 are 3-bit i/o ports and have basically the same functions as port p0. either cmos output or n-channel open-drain output structure can be selected as the port p3 0 and p3 1 . the output structure of port p3 2 is n-channel open-drain output. pins p3 0 , p3 1 are also used as analog input pins a-d5, a-d6 respectively. pins p3 0 , p3 1 are also used as d-a conversion output pins da1, da2 respectively. ports p3 3 , p3 4 are 2-bit input ports. p3 3 pin is also used as crt display clock input pin osc1. p3 4 pin is also used as crt display clock output pin osc2. the output structure is cmos output. ports p5 2 Cp5 5 are 4-bit output ports. the output structure is cmos output. pins p5 2 Cp5 5 are also used as crt output pins r, g, b, out respectively. the output structure is cmos output. this is a horizontal synchronous signal input for crt. this is a vertical synchronous signal input for crt. this is a 14-bit pwm output pin. i/o input i/o i/o i/o input output input input output output output input input output p2 0 /s clk , p2 1 /s out , p2 2 /s in , p2 3 /tim3, p2 4 /tim2, p2 5 Cp2 7 p3 0 /a-d5/ da1, p3 1 /a-d6/ da2, p3 2 p3 3 /osc1, p3 4 /osc2 p5 2 /r, p5 3 /g, p5 4 /b, p5 5 /out h sync v sync d-a i/o port p2 external clock input serial i/o synchronous clock input/ output serial i/o data input/output i/o port p3 analog input d-a conversion output input port p3 clock input for crt display clock output for crt display output port p5 crt output h sync input v sync input da output table 4.3.2 pin description (2) pin name input/ output functions
7220 m3-xxxsp/fp 4.4 functional block diagram 7220 group users manual 4-8 4.4 functional block diagram the functional block diagram is shown in figure 4.4.1. fig. 4.4.1 functional block diagram out clock input clock output x in x out reset input v cc v ss cnv ss clock output for display input ports p3 3, p3 4 osc1 osc2 clock input for display int2 int1 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 p5 (4) b g r h sync v sync a-d comparator 14-bit pwm circuit 8-bit pwm circuit accumulator a (8) timer 4 t4 (8) timer 3 t3 (8) timer 2 t2 (8) timer 1 t1 (8) timer count source selection circuit tim2 tim3 instruction register (8) instruction decoder control signal crt circuit stack pointer s (8) index register y (8) index register x (8) processor status register ps (8) 8-bit arithmetic and logical unit rom 12 k bytes program counter pc l (8) program counter pc h (8) ram 256 bytes data bus clock generating circuit reset output ports p5 2 Cp5 5 address bus si/o(8) s in s clk s out int3 10 9 8 7 6 5 4 3 i/o port p0 28 29 30 31 32 33 34 35 p1 (8) i/o port p1 15 14 13 12 11 36 37 38 p2 (8) i/o port p2 i/o ports p3 0 Cp3 2 17 26 27 16 p3 (3) p0 (8) 39 40 41 42 2 1 20 19 25 22 21 18 24 23 ( ) timing output d-a d-a converter
7220 m3-xxxsp/fp 4.5 functional description 4-9 7220 group users manual 4.5 functional description functions of m37220 m3-xxxsp/fp are partially different from those of m37221m6-xxxsp/fp. table 4.5.1 shows the difference between m37220 m3-xxxsp/fp and m37221m6-xxxsp/fp. table 4.5.1 difference between m37220 m3-xxxsp/fp and m37221m6-xxxsp/fp programmable i/o ports port p0 port p1 port p2 port p3 port p5 interrupts d-a converter multi-master i 2 c-bus interface crt display function number of display characters kinds of characters kinds of character back ground colors paramater m37221m6-xxxsp/fp 33 8 bits 8 bits 8 bits 8 bits 4 bits there is multi-master i 2 c-bus interface interrupt included 1 (2 systems) 24characters 5 2 lines 256 kinds possible (it can be specified by the character.) maximum 7 kinds m37220 m3-xxxsp/fp 33 8 bits 8 bits (functions except port are partially different.) 8 bits 8 bits (functions except port are partically different.) 4 bits no multi-master i 2 c-bus interface interrupt (priority level is the same as m37221m6-xxxsp/fp.) included 2 (6-bit resolution) 20 characters 5 2 lines 128 kinds not available
7220 m3-xxxsp/fp 4.5 functional description 7220 group users manual 4-10 4.5.1 access area figure 4.5.1 shows the m37220 m3-xxxsp/fp access area. fig. 4.5.1 access area 0000 16 00c0 16 00ff 16 013f 16 06b3 16 d000 16 sfr area special function register (refer to figures 4.5.3 and 4.5.4) not used not used ffff 16 ffde 16 ff00 16 0600 16 interrupt vector area not used 10000 16 10fff 16 1ffff 16 zero page crt display rom (4 k bytes) special page rom (12 k bytes) crt display ram (80 bytes) (note) ram (256 bytes) note: refer to table 4.5.7 contents of crt display ram. internal ram (192 bytes) ram for display internal rom internal ram (64 bytes) rom for display : internal rom area for program counter 65536 69631 131071
7220 m3-xxxsp/fp 4.5 functional description 4-11 7220 group users manual 4.5.2 memory assignment figure 4.5.2 shows the memory assignment m37220 m3-xxxsp/fp. fig. 4.5.2 memory assignment 0000 16 00c0 16 00ff 16 013f 16 06b3 16 d000 16 sfr area special function register (refer to figures 4.5.3 and 4.5.4) not used not used ffff 16 ffde 16 ff00 16 0600 16 interrupt vector area not used 10000 16 10fff 16 1ffff 16 zero page crt display rom (4 k bytes) special page rom (12 k bytes) crt display ram (80 bytes) (note) ram (256 bytes) note: refer to table 4.5.7 contents of crt display ram. internal ram (192 bytes) ram for display internal rom internal ram (64 bytes) rom for display hexadecimal notation decimal notation 0 255 319 1719 53248 65535 65502 65280 1536 192 65536 69631 131071
7220 m3-xxxsp/fp 4.5 functional description 7220 group users manual 4-12 fig. 4.5.3 memory map of sfr (special function register) (1) n sfr area (addresses c0 16 to df 16 ) d0 16 d1 16 d2 16 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 c0 16 c1 16 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c9 16 cb 16 cc 16 cd 16 ce 16 cf 16 ca 16 address port p5 (p5) port p5 direction register (d5) port p3 output mode control register (p3s) da-h register (da-h) da-l register (da-l) pwm0 register (pwm0) port p1 (p1) port p1 direction register (d1) port p3 (p3) port p3 direction register (d3) port p2 (p2) port p2 direction register (d2) register port p0 (p0) port p0 direction register (d0) pwm1 register (pwm1) pwm2 register (pwm2) pwm3 register (pwm3) pwm4 register (pwm4) pwm output control register 1 (pw) pwm output control register 2 (pn) serial i/o mode register (sm) serial i/o regsiter (sio) da1 conversion register (da1) da2 conversion register (da2) p30s p31s pw0 pw1 pw2 pw3 pw4 pw5 pw6 pw7 pn2 pn3 pn4 sm0 sm1 sm2 sm3 sm5 sm6 b7 b0 bit allocation state immediately after reset ? 00 16 b7 b0 ? 00 16 ? 00 16 ? ? ? ? ? 0 0 0 ? ? 0 0 ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? ? ? ? ? 00 16 ? ? ? ? ? ? 0 0 ? ? ?? ? ? 0 0 ? ? ?? ? ? ? da1s da2s da10 da11 da12 da13 da14 da15 da20 da21 da22 da23 da24 da25 ? 0 0 0 : 0 immediately after reset : undefined immediately after reset : fix this bit to 0 (do not write 1) 0 1 ? : < bit allocation > < state immediately after reset > function bit : no function bit : fix this bit to 1 (do not write 0) name : : 1 immediately after reset 1 0 00 16 00 16 00 16 00 16 00 16
7220 m3-xxxsp/fp 4.5 functional description 4-13 7220 group users manual fig. 4.5.4 memory map of sfr (special function register) (2) f0 16 f1 16 f2 16 f3 16 f4 16 f5 16 f6 16 f7 16 f8 16 f9 16 fa 16 fb 16 fc 16 fd 16 fe 16 ff 16 e0 16 e1 16 e2 16 e3 16 e4 16 e5 16 e6 16 e7 16 e8 16 e9 16 eb 16 ec 16 ed 16 ee 16 ef 16 ea 16 address crt control register (cc) crt port control register (crtp) a-d control register 1 (ad1) a-d control register 2 (ad2) timer 1 (tm1) vertical position register 2 (cv2) color register 0 (co0) color register 1 (co1) character size register (cs) border selection register (md) register horizontal position register (hr) vertical position register 1 (cv1) timer 2 (tm2) timer 3 (tm3) timer 4 (tm4) timer 12 mode register (t12m) timer 34 mode register (t34m) pwm5 register (pwm5) interrupt input polarity register (re) test register (test) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) color register 2 (co2) color register 3 (co3) crt clock selection register (ck) cpu mode register (cpum) b7 b0 bit allocation hr0 hr1 hr2 hr3 hr4 hr5 cv10 cv11 cv12 cv13 cv14 cv15 cv16 cv20 cv21 cv22 cv23 cv24 cv25 cv26 cs10 cs11 cs20 cs21 md10 md20 co01 co02 co03 co05 co11 co12 co13 co15 co21 co22 co23 co25 co31 co32 co33 co35 cc0 cc1 cc2 vsyc r/g/b out op5 op6 op7 hsyc ck0 ck1 adm0 adm1 adm2 adm4 adc0 adc1 adc2 adc4 adc3 adc5 t34m0 t34m1 t34m2 t34m3 t34m4 t12m0 t12m1 t12m2 t12m3 t12m4 ck0 re5 re4 re3 cm2 tm1r tm2r tm3r tm4r crtr vscr it3r ck0 msr 1t1r 1t2r s1r tm1e tm2e tm3e tm4e crte vsce it3e 1t1e 1t2e s1e mse t34m5 state immediately after reset ? b7 b0 0 ?????? ? 0 ?????? ? ???? 0000 ?? 00000 0 ? 00 16 00 00 0 0 ? 00 000 0 0 ff 16 07 16 ff 16 07 16 0 ? ? ? 00 00 0? 0 1 1 0 00 16 1 11 1 00 n sfr area (addresses e0 16 to ff 16 ) : 0 immediately after reset : undefined immediately after reset : fix this bit to 0 (do not write 1) 0 1 ? : < bit allocation > < state immediately after reset > function bit : no function bit : fix this bit to 1 (do not write 0) name : : 1 immediately after reset 1 0 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 0 00 00 16 11111 00 0 00 0 0 00 16 00 16 00 16 00 16
7220 m3-xxxsp/fp 4.5 functional description 7220 group users manual 4-14 4.5.3 input/output pins table 4.5.2 shows the difference of programmable ports between m37221m6-xxxsp/fp and m37220 m3- xxxsp/fp. table 4.5.2 difference of programmable ports between m37221m6-xxxsp/fp and m37220 m3- xxxsp/fp functions except port p0 0 Cp0 5 p0 6 p0 7 p1 0 p1 1 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p2 0 p2 1 p2 2 p2 3 p2 4 p2 5 Cp2 7 p3 0 p3 1 p3 2 p3 3 p3 4 p5 2 p5 3 p5 4 p5 5 port ] : it is the same as m37221m6-xxxsp/fp. m37220 m3-xxxsp/fp ] ] ] no function no function no function no function no function ] ] ] ] ] ] ] ] ] a-d5/da1 a-d6/da2 ] ] ] ] ] ] out m37221m6-xxxsp/fp pwm0Cpwm5 int2/a-d4 int1 out2 scl1 scl2 sda1 sda2 a-d1/int3 a-d2 a-d3 s clk s out s in tim3 tim2 a-d5 a-d6 osc1 osc2 r g b out1
7220 m3-xxxsp/fp 4.5 functional description 4-15 7220 group users manual vector addresses note: reset are included in the table because it operates in the same way as interrupts. the different interrupt-related registers from those of m37221m6-xxxsp/fp are shown in the following pages. 4.5.4 interrupts the m37220 m3-xxxsp/fp has 13 sources (reset is included) of interrupts. table 4.5.3 interrupt sources, vector addresses and priority priority 1 2 3 4 5 6 7 8 9 10 11 12 13 interrupt sources reset (note) crt interrupt int2 interrupt int1 interrupt timer 4 interrupt f(x in )/4096 interrupt vsync interrupt timer 3 interrupt timer 2 interrupt timer 1 interrupt serial i/o interrupt int3 interrupt brk instruction interrupt remarks non-maskable active edge selectable active edge selectable active edge selectable active edge selectable non-maskable (software interrupt) high-order byte ffff 16 fffd 16 fffb 16 fff9 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe5 16 ffdf 16 low-order byte fffe 16 fffc 16 fffa 16 fff8 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe4 16 ffde 16
7220 m3-xxxsp/fp 4.5 functional description 7220 group users manual 4-16 fig. 4.5.6 interrupt control register 1 (address 00fe 16 ) b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 1 (icon1) [address 00fe 16 ] b name functions after reset rw interrupt control register 1 0 timer 1 interrupt enable bit (tm1e) 0 : interrupt disabled 1 : interrupt enabled 0 1 timer 2 interrupt enable bit (tm2e) 0 2 timer 3 interrupt enable bit (tm3e) 0 3 timer 4 interrupt enable bit (tm4e) 0 4 crt interrupt enable bit (crte) 0 5 v sync interrupt enable bit (vsce) 0 6 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. 0 0 7 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled int3 interrupt enable bit (it3e) 0 : interrupt disabled 1 : interrupt enabled rw rw rw rw rw rw r rw fig. 4.5.5 interrupt request register 1 (address 00fc 16 ) b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 1 (ireq1) [address 00fc b name functions after reset rw interrupt request register 1 0 0 : no interrupt request issued 1 : interrupt request issued timer 1 interrupt request bit (tm1r) 1 timer 2 interrupt request bit (tm2r) 2 timer 3 interrupt request bit (tm3r) 3 timer 4 interrupt request bit (tm4r) 4 crt interrupt request bit (crtr) 5v sync interrupt request bit (vscr) 6 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. 7 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 0 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] ] : 0 can be set by software, but 1 cannot be set. int3 interrupt request bit (it3r) 0 : no interrupt request issued 1 : interrupt request issued ] 16 ] r r r r r r r r
7220 m3-xxxsp/fp 4.5 functional description 4-17 7220 group users manual d-a conversion is performed by setting the value in the da conversion register. the result of d-a conversion is output from the da pin by setting 1 to the da output enable bit of the port p3 output mode control register (bits 2 and 3 at address 00cd 16 ). the output analog voltage v is determined with the value n (n: decimal number) in the da conversion register. v=v cc 5 (n= 0 to 63) the da output does not build in a buffer, so connect an external buffer when driving a low-impedance load. table 4.5.4 relationship between contents of d-a conversion register and output voltage v bit 5 0 0 0 : 1 1 1 bit 4 0 0 0 : 1 1 1 bit 3 0 0 0 : 1 1 1 bit 1 0 0 1 : 0 1 1 a-d control register bit 0 0 1 0 : 1 0 1 bit 2 0 0 0 : 1 1 1 output voltage v 0/64 v cc 1/64 v cc 2/64 v cc : 61/64 v cc 62/64 v cc 63/64 v cc 4.5.5 d-a converter m37220 m3-xxxsp/fp has 2 d-a converter with 6-bit resolution. figure 4.5.7 shows the d-a converter block diagram. fig. 4.5.7 d-a converter block diagram data bus da1 output enable bit resistor ladder da1 conversion register p3 0 /a-d5/da1 (address 00de 16 ) 6 p3 1 /a-d6/da2 6 resistor ladder da2 conversion register (address 00df 16 ) da2 output enable bit n 64
7220 m3-xxxsp/fp 4.5 functional description 7220 group users manual 4-18 fig. 4.5.8 da n conversion register (addresses 00de 16 and 00df 16 ) fig. 4.5.9 port p3 output mode control register (address 00cd 16 ) b7 b6 b5 b4 b3 b2 b1 b0 da n conversion register (dan) (n = 1 and 2) [address 00de 16 , 00df 16 ] b after reset r w da n conversion register 0 to 5 6 indeterminate 0 name functions da conversion set bits (dan0Cdan5) b0 b1 b2 b3 b4 b5 fix this bit to 0. 1 000000 00000 0 0000 0 0 111 1 1 11111 1 111111 : 1/64vcc : 2/64vcc : 61/64vcc : 62/64vcc : 63/64vcc : 0/64vcc 7 0 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. rw r r 0 b7 b6 b5 b4 b3 b2 b1 b0 port p3 output mode control register (p3s) [address 00cd 16 ] b name functions after reset r w port p3 output mode control register 0 0 : cmos output 1 : n-channel open-drain output 0 1 0 0 4 to 7 0 p3 0 output structure selection bit (p30s) p3 1 output structure selection bit (p31s) nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 : cmos output 1 : n-channel open-drain output 2 da1 output enable bit (da1s) 0 : p3 0 input/output 1 : da1 output 0 3 da2 output enable bit (da2s) 0 : p3 1 input/output 1 : da2 output rw rw rw rw r
7220 m3-xxxsp/fp 4.5 functional description 4-19 7220 group users manual 4.5.6 crt display function table 4.5.5 shows the outline the crt display function of the m37220 m3-xxxsp/fp. table 4.5.5 outline of crt display function parameter number of display character dot structure kinds of character kinds of character sizes color display extension raster coloring kind of colors coloring unit performance 20 characters 5 2 lines 12 dots 5 16 dots 128 kinds 3 kinds 1 screen; 4 kinds, maximum 7 kinds a character possible (multiline display) possible (maximum 7 kinds)
7220 m3-xxxsp/fp 4.5 functional description 7220 group users manual 4-20 fig. 4.5.10 crt display circuit block diagram crt control register (address 00ea 16 ) vertical position registers (addresses 00e1 16 , 00e2 16 ) character size register (address 00e4 16 ) horizontal position register (address 00e0 16 ) border selection register (address 00e5 16 ) display oscillation circuit osc1 osc2 display position control circuit h sync v sync display control circuit ram for display 9 bits 5 20 characters 5 2 lines color registers (addresses 00e6 16 to 00e9 16 ) crt port control register (address 00ec 16 ) data bus rom for display 12 bits 5 16 dots 5 128 characters shift register 12 bits shift register 12 bits output circuit r g b out
7220 m3-xxxsp/fp 4.5 functional description 4-21 7220 group users manual (1) memory for display there are 2 types of display memory: crt display rom (addresses 10000 16 to 10fff 16 ) and crt display ram (addresses 0600 16 to 06b3 16 ). each type of display memory is described below. n crt display rom (addresses 10000 16 to 10fff 16 ) crt display rom has a capacity of 4 k bytes. since 32 bytes are required for 1 character data, the rom can stores up to 128 kinds of characters. crt display rom is broadly divided into 2 areas. the [vertical 16 dots] 5 [horizontal (left side) 8 dots] data of display characters are stored in addresses 10000 16 to 107ff 16 ; the [vertical 16 dots] 5 [horizontal (right side) 4 dots] data of display characters are stored in addresses 10800 16 to 10fff 16 (refer to figure 4.5.11 ). note however that the high-order 4 bits of the data to be written to addresses 10800 16 to 10fff 16 must be set to 1 (by writing data fx 16 ). fig. 4.5.11 example of display character data storing form 10xx0 16 +800 16 0000000 0000000 0000010 0000101 0001000 0001000 0001000 0010000 0 1 01 1111 001 0100000 0100000 0100000 0000000 0000101 0000010 0 1111 000 0 000 0 000 0 000 0 000 0 000 0 000 0 100 0 100 0 100 0 010 0 010 0 010 0 000 0 000 0 000 10xxf 16 +800 16 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 b7 b0 b7 b0 b3 10xx0 16 10xxf 16 0 0000 0 0 0 0 0 1 1 1 0 0 0 0 0 0
7220 m3-xxxsp/fp 4.5 functional description 7220 group users manual 4-22 block number block 1 block 2 character code 00 16 01 16 02 16 03 16 : 7e 16 7f 16 right 4 side 8 dots 10800 16 to 1080f 16 10810 16 to 1081f 16 10820 16 to 1082f 16 10830 16 to 1083f 16 : 10fe0 16 to 10fef 16 10ff0 16 to 10fff 16 left side 8 dots 10000 16 to 1000f 16 10010 16 to 1001f 16 10020 16 to 1002f 16 10030 16 to 1003f 16 : 107e0 16 to 107ef 16 107f0 16 to 107ef 16 the character code used to specify a display character is determined based on the address in the crt display rom in which that character data is stored. assume that 1 character data is stored in addresses 10xx0 16 to 10xxf 16 (xx denotes 00 16 to 7f 16 ) and 10yy0 16 to 10yyf 16 (yy denotes xx+800 16 ), then the character code is xx 16 . in other words, a character code is constructed with the low-order second and third digits (hexadecimal notation) of the 5-digit address (10000 16 to 107ff 16 ) where that character data is stored. a character code is yy 16 in addresses 11000 16 to 11fff 16 . table 4.5.6 shows the character code table. not used n crt display ram (addresses 0600 16 to 06b3 16 ) crt display ram is assigned to addresses 0600 16 to 06b3 16 . table 4.5.7 shows the contents of crt display ram. table 4.5.6 character code table (be omitted partly) character data stored address table 4.5.7 contents of crt display ram display position (from left side) 1st character 2nd character 3rd character : 18th character 19th character 20th character 1st character 2nd character 3rd character : 18th character 19th character 20th character 0600 16 0601 16 0602 16 : 0611 16 0612 16 0613 16 0614 16 to 061f 16 0620 16 0621 16 0622 16 : 0631 16 0632 16 0633 16 character code specifying color specifying 0680 16 0681 16 0682 16 : 0691 16 0692 16 0693 16 0694 16 : 069f 16 06a0 16 06a1 16 06a2 16 : 061 16 062 16 063 16
7220 m3-xxxsp/fp 4.5 functional description 4-23 7220 group users manual figure 4.5.12 shows the structure of crt display ram. fig. 4.5.12 structure of crt display ram [color specification] 0 0 : specifying color register 0 0 1 : specifying color register 1 1 0 : specifying color register 2 1 1 : specifying color register 3 color register specification 0 1 block 1 [character specification] specify 128 characters (00 16 to 7f 16 ) character code 70 block 2 [character specification] 1st character : 0620 16 20th character : 0633 16 1st character : 0680 16 20th character : 0693 16 1st character : 0600 16 20th character : 0613 16 70 [color specification] 1st character : 06a0 16 20th character : 06b3 16 0 1 to to to to specify 128 characters (00 16 to 7f 16 ) character code 0 0 : specifying color register 0 0 1 : specifying color register 1 1 0 : specifying color register 2 1 1 : specifying color register 3 color register specification
7220 m3-xxxsp/fp 4.5 functional description 7220 group users manual 4-24 the different crt display functionCrelated registers from those of m37221m6-xxxsp/fp are shown in the following pages. fig. 4.5.13 border selection register (addresses 00e5 16 ) fig. 4.5.14 color register n (addresses 00e6 16 to 00e9 16 ) b7 b6 b5 b4 b3 b2 b1 b0 color register n (con) (n = 0 to 3) [addresses 00e6 16 to 00e9 16 ] b name functions after reset r w color register n 0 0 1 b signal output selection bit (con1) 0 : no character is output 1 : character is output 0 2 g signal output selection bit (con2) 0 : no character is output 1 : character is output 0 3 r signal output selection bit (con3) 0 : no character is output 1 : character is output 0 4 5 out signal output control bit (con5) 0 : character is output 1 : blank is output 0 6, 7 0 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. 0 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. r rw rw rw r rw r b7 b6 b5 b4 b3 b2 b1 b0 border selection register (md) [address 00e5 16 ] b name functions after reset r w border selection register 0 block 1 out output border selection bit (md10) 0 : same output as character output 1 : border output indeterminate 1 2 block 1 out output border selection bit (md20) 0 : same output as character output 1 : border output 0 0 3 to 7 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. indeterminate rw r rw r
7220 m3-xxxsp/fp 4.5 functional description 4-25 7220 group users manual fig. 4.5.15 crt control register (address 00ea 16 ) b7 b6 b5 b4 b3 b2 b1 b0 crt control register (cc) [address 00ea 16 ] b name functions after reset r w crt control register 0 all-blocks display control bit (note) (cc0) 0 : all-blocks display off 1 : all-blocks display on 0 1 block 1 display control bit (cc1) 0 : block 1 display off 1 : block 1 display on 0 2 0 : block 2 display off 1 : block 2 display on 0 3 to 7 0 note: display is controlled by logical product (and) between the all-blocks display control bit and each block control bit. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. block 2 display control bit (cc2) rw rw rw r fig. 4.5.16 crt port control register (address 00ec 16 ) b7 b6 b5 b4 b3 b2 b1 b0 crt port control register (crtp) [address 00ec 16 ] b name functions after reset r w crt port control register 0h sync input polarity switch bit (hsyc) 0 : positive polarity 1 : negative polarity 0 1 0 : positive polarity 1 : negative polarity 0 2 r, g, b output polarity switch bit (r/g/b) 0 : positive polarity 1 : negative polarity 0 0 3 4 out output polarity switch bit (out) 0 : positive polarity 1 : negative polarity 0 5 r signal output switch bit (op5) 0 : r signal output 1 : mute signal output 0 6 g signal output switch bit (op6) 0 : g signal output 1 : mute signal output 0 7 b signal output switch bit (op7) 0 : b signal output 1 : mute signal output 0 v sync input polarity switch bit (vsyc) nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. rw rw rw r rw rw rw rw
7220 m3-xxxsp/fp 4.5 functional description 7220 group users manual 4-26 4.5.7 internal state immediately after reset figures 4.5.17 and 4.5.18 show the internal state immediately after reset. fig. 4.5.17 internal state immediately after reset (1) n sfr area (addresses c0 16 to df 16 ) d0 16 d1 16 d2 16 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 c0 16 c1 16 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c9 16 cb 16 cc 16 cd 16 ce 16 cf 16 ca 16 address port p5 (p5) port p5 direction register (d5) port p3 output mode control register (p3s) da-h register (da-h) da-l register (da-l) pwm0 register (pwm0) port p1 (p1) port p1 direction register (d1) port p3 (p3) port p3 direction register (d3) port p2 (p2) port p2 direction register (d2) register port p0 (p0) port p0 direction register (d0) pwm1 register (pwm1) pwm2 register (pwm2) pwm3 register (pwm3) pwm4 register (pwm4) pwm output control register 1 (pw) pwm output control register 2 (pn) serial i/o mode register (sm) serial i/o regsiter (sio) da1 conversion register (da1) da2 conversion register (da2) state immediately after reset ? 00 16 b7 b0 ? 00 16 ? 00 16 ? ? ? ? ? 0 0 0 ? ? 0 0 ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? ? ? ? ? 00 16 ? ? ? ? ? ? 0 0 ? ? ?? ? ? 0 0 ? ? ?? ? ? ? ? : 0 immediately after reset : undefined immediately after reset 0 1 ? < state immediately after reset > : 1 immediately after reset 00 16 00 16 00 16 00 16 00 16
7220 m3-xxxsp/fp 4.5 functional description 4-27 7220 group users manual fig. 4.5.18 internal state immediately after reset (2) f0 16 f1 16 f2 16 f3 16 f4 16 f5 16 f6 16 f7 16 f8 16 f9 16 fa 16 fb 16 fc 16 fd 16 fe 16 ff 16 e0 16 e1 16 e2 16 e3 16 e4 16 e5 16 e6 16 e7 16 e8 16 e9 16 eb 16 ec 16 ed 16 ee 16 ef 16 ea 16 address crt control register (cc) crt port control register (crtp) a-d control register 1 (ad1) a-d control register 2 (ad2) timer 1 (tm1) vertical position register 2 (cv2) color register 0 (co0) color register 1 (co1) character size register (cs) border selection register (md) register horizontal position register (hr) vertical position register 1 (cv1) timer 2 (tm2) timer 3 (tm3) timer 4 (tm4) timer 12 mode register (t12m) timer 34 mode register (t34m) pwm5 register (pwm5) interrupt input polarity register (re) test register (test) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) color register 2 (co2) color register 3 (co3) crt clock selection register (ck) cpu mode register (cpum) n sfr area (addresses e0 16 to ff 16 ) state immediately after reset ? b7 b0 0 ?????? ? 0 ?????? ? ???? 0000 ?? 00000 0 ? 00 16 ? 00 000 0 0 ff 16 07 16 ff 16 07 16 ? ? ? 00 00 0? 0 1 1 0 00 16 1 11 1 00 : 0 immediately after reset : undefined immediately after reset 0 1 ? < state immediately after reset > : 1 immediately after reset 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16
7220 m3-xxxsp/fp 4.6 electrical characteristics 7220 group users manual 4-28 4.6 electrical characteristics absolute maximum ratings notes 1: the total current that flows out of the ic must be 20 ma (max.). 2: the total input current to ic (i ol1 + i ol2 ) must be 30 ma or less. 3: the total average input current for ports p2 4 Cp2 7 to ic must be 20 ma or less. symbol v cc v i v i v o v o i oh i ol1 i ol2 i ol3 p d t opr t stg parameter power source voltage v cc input voltage cnv ss input voltage p0 0 Cp0 7 ,p1 0 Cp1 7 , p2 0 C p2 7 , p3 0 Cp3 4 , osc1, x in , h sync , v sync , reset output voltage p0 6 , p0 7 , p1 0 Cp1 7 , p2 0 C p2 7 , p3 0 Cp3 2 , r, g, b, out, d-a, x out , osc2 output voltage p0 0 Cp0 5 circuit current r, g, b, out, p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , d-a circuit current r, g, b, out1, p0 6 , p0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p3 0 C p3 2 , d-a circuit current p0 0 Cp0 5 circuit current p2 4 Cp2 7 power dissipation operating temperature storage temperature conditions all voltages are based on v ss . output transistors are cut off. t a = 25 c ratings C0.3 to 6 C0.3 to 6 C0.3 to v cc + 0.3 C0.3 to v cc + 0.3 C0.3 to 13 0 to 1 (note 1) 0 to 2 (note 2) 0 to 1 (note 2) 0 to 10 (note 3) 550 C10 to 70 C40 to 125 unit v v v v v ma ma ma ma mw c c
7220 m3-xxxsp/fp 4.6 electrical characteristics 4-29 7220 group users manual v cc v ss v ih v il1 v il2 i oh i ol1 i ol2 i ol3 f(x in ) f crt f hs1 f hs2 power source voltage (note 4), during cpu, crt operation power source voltage high input voltage p0 0 Cp0 7 ,p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 4 , s in , s clk , h sync , v sync , reset, x in , osc1, tim2, tim3, int1, int2, int3 low input voltage p0 0 Cp0 7 ,p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 4 low input voltage h sync , v sync , reset, tim2, tim3, int1, int2, int3, x in , osc1, s in , s clk high average output current (note 1) r, g, b, out, d-a, p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 low average output current (note 2) r, g, b, out, d-a, p0 6 , p0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 2 low average output current (note 2) p0 0 Cp0 5 low average output current (note 3) p2 4 Cp2 7 oscillation frequency (for cpu operation) (note 5) x in oscillation frequency (for crt display) (note 5) osc1 input frequency tim2, tim3 input frequency s clk recommended operating conditions (t a = C10 c to 70 c, v cc = 5 v 10 %, unless otherwise noted) parameter symbol notes 1: the total current that flows out of the ic must be 20 ma (max.). 2: the total input current to ic (i ol1 + i ol2 ) must be 30 ma or less. 3: the total average input current for ports p2 4 Cp2 7 to ic must be 20 ma or less. 4: connect 0.1 f or more capacitor externally across the power source pins v cc Cv ss so as to reduce power source noise. also connect 0.1 f or more capacitor externally across the pins v cc Ccnv ss . 5: use a quartz-crystal oscillator or a ceramic resonator for the cpu oscillation circuit. max. 5.5 0 v cc 0.4v cc 0.2v cc 1 2 1 10 8.1 8.0 100 1 min. 4.5 0 0.8v cc 0 0 7.9 5.0 typ. 5.0 0 8.0 v v v v v v ma ma ma ma mhz mhz khz mhz unit
7220 m3-xxxsp/fp 4.6 electrical characteristics 7220 group users manual 4-30 v cc = 5.5 v, f(x in ) = 8 mhz v cc = 5.5 v, f(x in ) = 0 v cc = 4.5 v i oh = C0.5 ma v cc = 4.5 v i ol = 0.5 ma v cc = 4.5 v i ol = 10.0 ma v cc = 5.0 v v cc = 5.0 v v cc = 5.5 v v i = 5.5 v v cc = 5.5 v v i = 0 v v cc = 5.5 v v o = 12 v power source current high output voltage r, g, b, out, d-a, p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 low output voltage r, g, b, out, d-a, p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 2 low output voltage p2 4 Cp2 7 hysteresis reset hysteresis (note) h sync , v sync , tim2, tim3, int1, int2, int3, s in , s clk high input leak current reset, p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 4 , h sync , v sync low input leak current reset, p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 4 , h sync , v sync high output leak current p0 0 Cp0 5 electric characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = C10 c to 70 c, unless otherwise noted) test conditions i cc v oh v ol v t+ Cv tC i izh i izl i ozh parameter symbol system operation stop mode crt off crt on ma a v v v a a a max. 40 60 300 0.4 3.0 0.7 1.3 5 5 10 min. 2.4 typ. 20 30 0.5 0.5 limits unit note: p0 6 , p0 7 , p1 5 , p2 3 and p2 4 have the hysteresis when these pins are used as interrupt input pins or timer input pins. p2 0 Cp2 2 have the hysteresis when these pins are used as serial i/o pins.
7220 m3-xxxsp/fp 4.6 electrical characteristics 4-31 7220 group users manual a-d comparator characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = C10 c to 70 c, unless otherwise noted) note: when v cc = 5 v, 1 lsb = 5/64 v. d-a converter characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = C10 c to 70 c, unless otherwise noted) limits unit bits lsb typ. 1 max. 6 2 min. 0 parameter symbol test conditions resolution absolute accuracy limits unit bits % s k w typ. 2.5 max. 6 2 3 4 min. 1 parameter symbol test conditions t su r o resolution absolute accuracy setting time output resistor
7220 m3-xxxsp/fp 4.7 standard characteristics 7220 group users manual 4-32 4.7 standar d c haracteristics the data described in this section are characteristic exampl es. refer to 4.6 electrical characteristics for rated values. 100.00 0.000 0.000 low level output voltage v ol [v] low level output current i ol [ma] v cc =5.5v v cc =4.5v 6.00 0 4.800 3.600 2.400 1.200 1. ports p0 0 Cp0 5 and p3 2 (a) i ol Cv ol characteristics 20.00 40.00 60.00 80.00 100.00 0.000 0.000 low level output voltage v ol [v] high level output current i oh [ma] v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 2. ports p 0 6 and p0 7 (a) i oh Cv ol characteristics 20.00 40.00 60.00 80.00
7220 m3-xxxsp/fp 4.7 standard characteristics 4-33 7220 group users manual 100.00 0.000 0.000 v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 3. ports p1 0 Cp1 7 , p2 0 Cp2 3 , p3 0, p3 1 and d-a (a) i ol Cv ol characteristics 20.00 40.00 60.00 80.00 C 100.00 0.000 0.000 high level output voltage v oh [v] high level output current i oh [ma] v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 (b) i ohC v oh characteristics 20.00 40.00 60.00 80.00 low level output voltage v ol [v] low level output current i ol [ma] C C C C C CC CC
7220 m3-xxxsp/fp 4.7 standard characteristics 7220 group users manual 4-34 100.00 0.000 0.000 low level output voltage v ol [v] low level output current i ol [ma] v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 4. ports p2 4 Cp2 7 (a) i olC v ol characteristics 20.00 40.00 60.00 80.00 100.00 0.000 0.000 high level output voltage v oh [v] high level output current i oh [ma] v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 (b) i oh Cv oh characteristics 20.00 40.00 60.00 80.00 C C C C C C CC C C
7220 m3-xxxsp/fp 4.7 standard characteristics 4-35 7220 group users manual 100.00 0.000 0.000 low level output voltage v ol [v] low level output current i ol [ma] v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 5. ports p5 2 Cp5 5 (a) i olC v ol characteristics 20.00 40.00 60.00 80.00 100.00 0.000 0.000 high level output voltage v oh [v] high level output current i oh [ma] v cc =5.5v v cc =4.5v 6.000 4.800 3.600 2.400 1.200 (b) i oh Cv oh characteristics 20.00 40.00 60.00 80.00 C C C C C C C C C C
7220 m3-xxxsp/fp) 5.3 usage example of rom correction function (m37221m8/ma-xxxsp) 5.4 example of i 2 c-bus interface control (m37221mx-xxxsp/fp) 5.5 example of i 2 c-bus interface control by software (m37220 m3-xxxsp/fp) 5.6 application circuit example
7220 group users manual 5-2 fig. 5.1.2 display example 5.1 example of multi-line display the m37221mx-xxxsp/fp is used as a general example in describing this application for the 7220 group. the m377221mx-xxxsp/fp ordinarily displays 2 lines on a crt screen by displaying 2 blocks at different vertical positions. in addition to this, it can display 3 lines or more (multi-line display) by rewriting both character data and display positions during interrupt processing, using crt interrupts. an example of the software processing for implemention this multi-line display is described below. this example is 12-line multi-line display using blocks 1 and 2. for crt display details, refer to 2.11 crt display function. 5.1.1 specifications l pins required: r, g, b, out1, h sync , and v sync l h sync /v sync input polarity: positive polarity input l r/g/b/out1 output polarity: positive polarity output l character colors: red, blue, white, and cyan l no character background color l bordering (out) is available l character size: minimum size l 12-line display 5.1.2 connection example fig. 5.1.1 connection example p5 2 /r p5 3 /g p5 4 /b p5 5 /out1 h sync v sync m37221mx-xxxsp/fp monitor color tv signal processor c a l e n d a r sun. 3 1 0 1 7 2 4 3 1 mon. 4 1 1 1 8 2 5 tues. 5 1 2 1 9 2 6 wed. 6 1 3 2 0 2 7 thur. 7 1 4 2 1 2 8 fri. 1 8 1 5 2 2 2 9 sat. 2 9 1 6 2 3 3 0 ? the 1st line ? the 2nd line ? the 3rd line ? the 4th line ? the 5th line ? the 6th line ? the 7th line ? the 8th line ? the 9th line ? the 10th line ? the 11th line ? the 12th line block 1 block 2 block 1 block 2 block 1 block 2 block 1 block 2 block 1 block 2 block 1 block 2 blue (b) red (r) cyan (r+g) white (r+g+b) j a n
7220 group users manual 5.1.3 general flowchart the multi-line display processing routine consists of initialization processing routine, v sync interrupt processing routine, and crt interrupt processing routine. (1) initialization processing routine this routine is used to initialize to cause a crt interrupt. fig. 5.1.3 flowchart of initialization processing routine cs (address 00e4 16 ) md (address 00e5 16 ) hr (address 00e0 16 ) ck (address 00ed 16 ) multi-line display start end cv2 (address 00e2 16 ) ? vertical display start position of the 12th line (block 2) line counter f_vsync block 1 display ram ? display character (blank) of block 1 (addresses 0600 16 to 0617 16 ) character color (no output) of block 1 (addresses 0680 16 to 0697 16 ) enable crt interrupt in synchronized with the next v sync character size : minimum size border output set a horizontal display start position set display clock disable only crt interrupt all blocks display off select r/g/b/out1 h sync /v sync input polarity : positive polarity input r/g/b/out1 output polarity : positive polarity output color register 0 : red color register 1 : blue color register 2 : white color register 3 : cyan ? 00000000 2 ? 00000101 2 ? xxxxxxxx 2 ? 00000010 2 counter ram for line counting vertical position registers 1, 2 port p5 direction register crt port control register crt control register color registers 0 to 3 v sync flag border selection register crt clock selection register line counter : cv1, cv2 : p5d : crtp : cc : co0 to co3 : f_vsync : md : ck : initialization ? 0 ? 00000000 2 ? 00000000 2 ? 00000000 2 ? 00001000 2 (red) ? 00000010 2 (blue) ? 00001110 2 (white) ? 00000110 2 (cyan) crte (bit4 at address 00fe 16 ) cc (address 00ea 16 ) p5d (address 00cb 16 ) crtp (address 00ec 16 ) co0 (address 00e6 16 ) co1 (address 00e7 16 ) co2 (address 00e8 16 ) co3 (address 00e9 16 ) block 2 display ram ? display character (blank) of block 2 (addresses 0620 16 to 0637 16 ) character color (no output) of block 2 (addresses 06a0 16 to 06b7 16 ) cv1 (address 00e1 16 ) ? vertical display start position of the 11th line (block 1) ? 0 ? 1 bit 4 of interrupt control register 1 bit 4 of interrupt request register 1 character size register horizontal position register crte : crtr : cs : hr : note: this routine is not interrupt processing routine.
7220 group users manual 5-4 (2) v sync interrupt processing routine the v sync interrupt processing routine consists of; multi-line display start processing and multi-line display correction processing. the correction processing corrects erroneous multi-line display due to various influences. fig. 5.1.4 flowchart of v sync interrupt processing routine v sync interrupt processing routine cc : line counter : f_vsync : cv1,cv2 : v_icon1, v_icon2 : a : x : y : t : d : crt control register counter ram for line counting v sync flag vertical position registers 1, 2 back up ram for interrupt control registers 1, 2 during v sync interrupt accumulator index register x index register y x modified operation mode flag decimal operation mode flag ? 0 ? 0 ? icon1 ? icon2 ? 00000001 2 ? 00000000 2 ? 0 t d v_icon1 v_icon2 icon1 (address 00fe 16 ) icon2 (address 00ff 16 ) i push registers x, y, a f_vsync crtr (bit 4 at address 00fe 16 ) crte (bit 4 at address 00fc 16 ) cc (address 00ea 16 ) f_vsync =0 ? enable crt interrupt =1 ? all blocks display on return setting for multiple interrupts pass this process only once at display start. ? 0 ? 0 ? 1 ? 07 16 line counter ? 2 cv1 ? vertical display start position of the 1st line (block 1) cv2 ? vertical display start position of the 2nd line (block 2) crtr (bit 4 at address 00fe 16 ) ? 0 pop registers x, y, a i icon1 icon2 ? 1 ? v_icon1 ? v_icon2 setting for multiple interrupts ? push icon1 contents during v sync interrupt ? push icon2 contents during v sync interrupt ? enable only timer 1 interrupt ? enable multipule interrupt set by steps , (refer to 5.1.7 (2) ) ? disable all interrupts note: the multiple interrupt priority of this system sync > crt correction for erroneous multi-line display (refer to 5.1.6 ) ? pop icon 1 and 2 contents during sync interrupt (refer to 5.1.7 (2) ) c icon1, icon2: crte : crtr : interrupt control registers 1, 2 bit 4 of interrupt control register 1 bit 4 of interrupt request register 1 v interrupt is as below. timer 1 > v
7220 group users manual (3) crt interrupt processing routine the crt interrupt processing routine executes the display character data setup routine for each line, in order to perform multi-line display. the line to be displayed is determined by the line counter value. fig. 5.1.5 flowchart of crt interrupt processing routine crt interrupt processing routine ? specify jump destination by line counter value return line counter +1 line counter =12 line counter ? 0 save the value of line counter in internal ram pop registers x, y, a i icon1 icon2 =12 1 12 ? 0 ? 0 ? icon1 ? icon2 ? 00100001 2 ? 00000000 2 ? 0 t d crt_icon1 crt_icon2 icon1 (address 00fe 16 ) icon2 (address 00ff 16 ) i push registers x, y, a icon1, icon2: cs : hr : line counter : cv1,cv2 : crt_icon1, crt_icon2 : a : x : y : t : d : interrupt control registers 1, 2 character size register horizontal position register counter ram for line counting vertical position registers 1, 2 back up ram for interrupt control registers 1, 2 during crt interrupt accumulator index register x index register y x modified operation mode flag decimal operation mode flag ? disable all interrupts note: the multiple interrupt priority of sync > crt ? 1 ? crt_icon1 ? crt_icon2 ? pop icon 1 and 2 contents during interrupt (refer to 5.1.7 (2) ) ? enable timer 1 interrupt and v sync interrupt line counter = 0 = 1 set cs, hr block 1 display ram ? display character of block 1 (the 1st line) character color of block 1 (the 1st line) cv1 ? vertical display start position of the 1st line (block 1) set cs, hr block 2 display ram ? display character of block 2 (the 2nd line) character color of block 2 (the 2nd line) = 11 set cs, hr block 2 display ram ? display character of block 2 (the 12th line) character color of block 2 (the 12th line) cv2 ? vertical display start position of the 2nd line (block 2) cv2 ? vertical display start position of the 12th line (block 2) crt this system is as below. timer 1 > v
7220 group users manual 5-6 5.1.4 set of display character data to display the character data, set the character codes (00 16 to ff 16 ) in the character addresses (block 1: addresses 0600 16 to 0617 16 , block 2: addresses 0620 16 to 0637 16 ). also, set the color register specifying (00 2 to 11 2 ) in the color addresses (block 1: addresses 0680 16 to 0697 16 , block 2: addresses 06a0 16 to 06b7 16 ). fig. 5.1.6 set of display character data character code (00 16 to ff 16 ) character addresses 0600 16 0601 16 0680 16 0681 16 0616 16 0617 16 0696 16 0697 16 block 1 0620 16 0621 16 06a0 16 06a1 16 0636 16 0637 16 06b6 16 06b7 16 block 2 24 characters character code (001 16 to ff 16 ) character addresses 24 characters color addresses color register specifying (00 2 to 11 2 ) color addresses color register specifying (00 2 to 11 2 )
7220 group users manual 5.1.5 line counter the line counter determines which line of display data is to be set. for example, if a crt interrupt occurs at the end of the first line display, the line counter value will be 2. therefore, the 3rd line display data must be set from the end of the 1st line display to the start of the 3rd line display. then, the line counter value is incremented and becomes 3. figure 5.1.7 shows the example of the setup timing for the line counter and the display character data. fig. 5.1.7 example of setup timing for line counter and display character data the 1st line (block 1) the 2nd line (block 2) the 3rd line (block 1) the 11th line (block 1) line counter value 2 3 4 0 line counter value : 2 crt interrupt set 3rd line display data by the start of 3rd line display line counter value: 3 the 12th line (block 2) 1 ... the 4th line (block 2) a start of the 3rd line display end of the 1st line display
7220 group users manual 5-8 5.1.6 processing time when setting display data by a crt interrupt, the processing time is limited. as shown in figure 5.1.7, a crt interrupt occurs at the end of the first line (block 1) display and setting for the 3rd line display is started. this setting must be completed before a scanning line reaches to the 3rd line display position. if the setting is not completed, display characters flicker or rewriting is looked. and also, for multi-line display of 12 lines, be sure that crt interrupts occur 12 times from a v sync to the next v sync . if crt interrupts do not occur as many times as the number of display lines, the following causes can be assumed. ? display position overlaps. ? crt interrupt processing time is too long, resulting in no display of that line (2 lines after the line being displayed). for example, a crt interrupt occurs at the end of the second line display in figure 5.1.7. within this interrupt processing, setting for the 4th line display is completed. however, if a scanning line is over the display position of the 4th line (that is, a in figure 5.1.7) during this setting, one crt interrupt request is deleted (or does not occur). therefore, the line counter value is disordered and multi-line display is not displayed correctly. in such cases, due to whatever causes, correct the value with processing c of v sync interrupt processing (refer to figure 5.1.4 ). when the crt interrupt software processing overtime causes this state, change the display positions or shorten the crt interrupt software processing time.
7220 group users manual 5.1.7 set of multiple interrupts (1) when not setting multiple interrupts when two or more interrupt requests occur at the same sampling point, the interrupt with the higher priority (refer to 2.5 interrupts, table 2.5.1 ) is received. this priority level is determined by hardware but various priority processing by software can be executed using the interrupt enable bit and each interrupt disable flag (i). assume, for example, that all interrupts (crt, v sync , timer 1) are enabled. when the multiple interrupt is not set, these interrupt request bits are set to 1 and the interrupts are determined by hardware as follows: crt interrupt v sync interrupt a timer 1 interrupt figure 5.1.8 shows the timing of interrupt processing when not setting multiple interrupts. the i flag is set to 1 (all interrupts are disabled) automatically by hardware as soon as the interrupt processing starts. unless the i flag is cleared to 0, other interrupt will not occur during the interrupt processing. fig. 5.1.8 timing of interrupt processing when not setting multiple interrupts crt interrupt request bit v sync interrupt request bit timer 1 interrupt request bit crt interrupt processing v sync interrupt processing timer 1 interrupt processing interrupt disable flag (i) 1 0 1 0 1 0 1 2 3 3
7220 group users manual 5-10 (2) when setting multiple interrupts various priority processings are executed by enabling multiple interrupts and by setting priorities by software. for example, to set the priority listed below; timer 1 interrupt v sync interrupt a crt interrupt execute the following process: set only interrupt enable bits (icon1, icon2) whose priorities are higher than the current interrupt, and enable the interrupt disable flag (i) in only the current interrupt processing routine. figure 5.1.9 shows the timing when all interrupt request bits (crt, v sync , timer 1) are 1 at the same sampling point. note: when setting multiple interrupts, be sure to determine priority levels to prevent occurrence of plural interrupts with the same priority level. fig. 5.1.9 timing when all interrupt request bits are 1 at the same sampling point crt interrupt request bit v sync interrupt request bit timer 1 interrupt request bit crt interrupt processing v sync interrupt processing timer 1 interrupt processing interrupt disable flag (i) 1 0 1 0 1 0 a b 1 1 a (series of ) 3 b 3 (series of ) 3 (series of ) 2 2
7220 group user? manual (3) crt interrupt processing routine when setting multiple interrupts figure 5.1.10 shows the flowchart of crt interrupt processing routine when setting multiple interrupts. a and b are the setting routines for multiple interrupts. fig. 5.1.10 flowchart of crt interrupt processing routine (when setting multiple interrupts) crt interrupt processing routine return crt interrupt processing i icon1 icon2 ? icon1 ? icon2 ? ?0100001 2 ? ? ?0000000 2 ? ? ? crt_icon1 crt_icon2 icon1 (address 00fe 16 ) icon2 (address 00ff 16 ) i push registers x, y, a icon1, icon2: crt_icon1, crt_icon2 : a : x : y : t : d : interrupt control registers 1, 2 back up ram for interrupt control registers 1, 2 during crt interrupt accumulator index register x index register y x modified operation mode flag decimal operation mode flag ? disable all interrupts ? ? ? crt_icon1 ? crt_icon2 ? ? ? ?? t d a set routine for multiple interrupts pop the registers x, y, a b disable multiple interrupts ? enable v sync and timer 1 interrupts to take priority than crt interrupt. and also, be sure to disable the following interrupts: -crt interrupt -all interrupts with lower priority than crt interrupt. ? pop icon 1 and 2 contents during crt interrupt enable state of multiple interrupts (v sync , timer 1)
7220 group user? manual 5-12 (4) v sync interrupt processing routine when setting multiple interrupts figure 5.1.11 shows the flowchart of v sync interrupt processing routine when setting multiple interrupts. a?and b?are the setting routines for multiple interrupts. fig. 5.1.11 flowchart of v sync interrupt processing routine (when setting multiple interrupts) v sync interrupt processing routine return v sync interrupt processing i icon1 icon2 ? icon1 ? icon2 ? ?0000001 2 ? ? ?0000000 2 ? ? ? v_icon1 v_icon2 icon1 (address 00fe 16 ) icon2 (address 00ff 16 ) i push registers x, y, a icon1, icon2: v_icon1, v_icon2 : a : x : y : t : d : interrupt control registers 1, 2 back up ram for interrupt control registers 1, 2 during v sync interrupt accumulator index register x index register y x modified operation mode flag decimal operation mode flag ? disable all interrupts ? ? ? v_icon1 ? v_icon2 ? pop icon 1 and 2 contents during v sync interrupt ? ? ? ?? t d a set routine for multiple interrupts pop the registers x, y, a disable multiple interrupts ? enable timer 1 interrupt to take priority than v sync interrupt. and also, be sure to disable the following interrupts: -v sync interrupt -all interrupts with lower priority than v sync interrupt. b enable state of multiple interrupts (timer 1)
7220 m3-xxxsp/fp) 7220 group users manual 5-13 5.2 notes on programming for osd (m37220 m3-xxxsp/fp) the emulator mcu m37221erss is used for programming development with the m37220 m3-xxxsp/fp. however, the functions of the m37221erss are compatible with those of the m37221mx-xxxsp/fp, and therefore has some functions which the m37220 m3-xxxsp/fp does not have. note the following differences when programming using the m37220 m3-xxxsp/fp. 5.2.1 setting of color registers the color registers of m37220 m3-xxxsp/fp are different from those of m37221erss (refer to figures 5.2.1 and 5.2.2 ). character background colors can be output when programming with the m37221erss, but not with the m37220 m3-xxxsp/fp mask version. this character background color program does not operate on the m37220 m3-xxxsp/fp and therefore, it cannot output character background colors (except character background colors by out signal; bit 5). fig. 5.2.1 color register n (m37221erss) b7 b6 b5 b4 b3 b2 b1 b0 color register n (co0 to co3) (n = 0 to 3) [addresses 00e6 16 to 00e9 16 ] b name functions after reset r w color register n 0 0 1 b signal output selection bit (con1) 0 : no character is output 1 : character is output 0 2 g signal output selection bit (con2) 0 : no character is output 1 : character is output 0 3 r signal output selection bit (con3) 0 : no character is output 1 : character is output 0 4 b signal output (background) selection bit (con4) 0 : no background color is output 1 : background color is output 0 5 out1 signal output control bit (con5) 0 : character is output 1 : blank is output 0 6 g signal output (background) selection bit (con6) 0 : no background color is output 1 : background color is output 0 7 r signal output (background) selection bit (con7) 0 : no background color is output 1 : background color is output 0 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. (see note 1) (see notes 1, 2) (see note 2) notes 1: when bit 5 = 0 and bit 4 = 1, there is output same as a character or border output from the out1 pin. do not set bit 5 = 0 and bit 4 = 0. 2: when only bit 7 = 1 and bit 5 = 0, there is output from the out2 pin. r rw rw rw rw rw rw rw
7220 m3-xxxsp/fp) 7220 group users manual 5-14 fig. 5.2.2 color register n (m37220 m3-xxxsp/fp) b7 b6 b5 b4 b3 b2 b1 b0 color register n (con) (n = 0 to 3) [addresses 00e6 16 to 00e9 16 ] b name functions after reset r w color register n 0 0 1 b signal output selection bit (con1) 0 : no character is output 1 : character is output 0 2 g signal output selection bit (con2) 0 : no character is output 1 : character is output 0 3 r signal output selection bit (con3) 0 : no character is output 1 : character is output 0 4 5 out signal output control bit (con5) 0 : character is output 1 : blank is output 0 6, 7 0 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. 0 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. r rw rw rw r rw r 5.2.3 number of display characters the m37221erss can display up to 24 characters in each block. however, the m37220 m3-xxxsp/fp can display only up to 20 characters in each block. note this when programming using the m37220 m3-xxxsp/ fp. 5.2.2 setting border selection register the m37220 m3-xxxsp/fp can output neither character background (out) nor border at the same time. when setting the border selection bits (bit 0 or 2) to 1, the border output takes over out (setting of bit 5 of the color registers). therefore, select either the character background output or the border output. fig. 5.2.3 border selection register (m37220 m3-xxxsp/fp) b7 b6 b5 b4 b3 b2 b1 b0 border selection register (md) [address 00e5 16 ] b name functions after reset r w border selection register 0 block 1 out output border selection bit (md10) 0 : same output as character output 1 : border output indeterminate 1 2 block 2 out output border selection bit (md20) 0 : same output as character output 1 : border output 0 0 3 to 7 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. indeterminate rw r rw r
7220 group user? manual 5-15 5.3.2 correction example the following is an example when 2 addresses (2 blocks) of rom are corrected. (1) correction example 1 5.3 usage example of rom correction function (m37221m8/ma-xxxsp) application example using the rom correction function is described below. in this example, it is assumed that the program must be changed by specifications modification after completion of rom mask. also, e 2 prom is connected to this system. 5.3.1 connection example fig. 5.3.1 connection example fig. 5.3.2 correction example (1) i 2 c-bus m6m80012p m37221m8-xxxsp m37221ma-xxxsp lda dec sta dec dec 02c0 02c2 02c3 02c6 02c7 02ca a980 1a 8d1201 1a 8d1301 4c26e1 address (block 1) lda inc a sta rts a900 3a 8d1101 60 e120 e122 e123 e126 address machine instructions description style program before correction machine instructions description style correction program note: in , e126h is specified as the return destination address of jmp . rts , rts is used instead of jmp , the operation is the same as that of jmp . as a result, the number of bytes is reduced. jmp (see note) in this example, since the instruction at the return destination address is even if #00h 0111h #80h a 0112h a 0113h e126h
7220 group user? manual 5-16 (2) correction example 2 the loop processing is performed between and a in figure 5.3.3. two examples of this part are shown in detail. example a corrects in loop units and example b corrects only error instructions. examples a and b are the same operation, differing in processing time and correction bytes only. depending on the contents of loop processing, it may be preferable to include correct codes with the codes to be corrected, simplifying the correction program and making it easier to read. when omitting fe96h ( ? ) and correcting from fe98h, the program cannot move to fe96h by the bpl instruction (the jump destination addresses of the bpl instruction are limited to bytes between ?28 and +127). therefore, the example b is provided. fig. 5.3.3 correction example (2) fe96 fe98 fe99 fe9b 9525 ca 10fb 60 sta dex bpl a (see note 2) rts address machine instructions description style program before correction notes 1: in , fe9bh is specified as the return destination address of jmp . rts , rts is used instead of jmp , the operation is the same as that of jmp . as a result, the number of bytes is reduced. 2: bpl and bmi , as machine instructions, have no absolute addresses, but relative machine instructions description style correction program example a 9d2501 3a ca 3003 4c96fe 4c9bfe sta inc dex bmi (see note 2) jmp jmp (see note 1) correction program example b 9525 9d2501 3a ca 10f7 60 sta ? sta inc dex bpl ? (see note 2) rts (see note 1) 02e0 02e2 02e5 02e6 02e7 02e9 address (block 2) machine instructions description style 02e0 02e3 02e4 02e5 02e7 02ea address (block 2) in this example, since the instruction at the return destination address is even if addresses as branch destinations. 025h, x 0fe96h 025h, x 0125h, x a 02e0h 0125h, x a 02eah fe96h fe9bh
7220 group user? manual 5-17 fig. 5.3.4 e 2 prom map when using rom correction function (1) 5.3.3 e 2 prom map figures 5.3.4 and 5.3.5 show the e 2 prom map when using the rom correction function. to store correction codes by using both rom correction functions 1 and 2, the capacity of e 2 prom needs to be approximately 70 bytes. e 2 prom address 000 16 contents instructions in correction program stored data (machine instruction) rom correction function 1 (55h: valid, others: invalid) 55h 001 16 rom correction function 1 execution address (high-order) e1h 002 16 rom correction function 1 execution address (low-order) 20h 003 16 rom correction function 1 80h correction code 1 004 16 rom correction function 1 1ah correction code 2 005 16 rom correction function 1 8dh correction code 3 006 16 rom correction function 1 12h correction code 4 007 16 rom correction function 1 01h correction code 5 008 16 rom correction function 1 1ah correction code 6 009 16 rom correction function 1 8dh dec a correction code 7 00a 16 rom correction function 1 13h sta 0113h correction code 8 00b 16 rom correction function 1 01h correction code 9 00c 16 rom correction function 1 4ch correction code 10 00d 16 rom correction function 1 26h jmp e126h correction code 11 00e 16 rom correction function 1 e1h correction code 12 00f 16 rom correction function 1 correction code 13 010 16 rom correction function 1 eah nop (see note) correction code 14 011 16 rom correction function 1 eah nop correction code 15 012 16 rom correction function 1 eah nop correction code 16 013 16 rom correction function 1 eah nop correction code 17 014 16 rom correction function 1 eah nop correction code 18 015 16 rom correction function 1 eah nop correction code 19 016 16 rom correction function 1 eah nop correction code 20 017 16 rom correction function 1 eah nop correction code 21 018 16 rom correction function 1 eah nop correction code 22 019 16 rom correction function 1 eah nop correction code 23 01a 16 rom correction function 1 eah nop correction code 24 01b 16 rom correction function 1 eah nop correction code 25 01c 16 rom correction function 1 eah nop correction code 26 01d 16 rom correction function 1 eah nop correction code 27 01e 16 rom correction function 1 eah nop correction code 28 01f 16 rom correction function 1 eah nop correction code 29 020 16 rom correction function 1 4ch jmp yyxxh set reset vector address to yyxxh (see note). correction code 30 021 16 rom correction function 1 xxh correction code 31 022 16 rom correction function 1 yyh correction code 32 a9h sta 0112h dec a lda #80h refer to ?igure 5.3.2 note: when operating normally, this instruction is not executed. this is a redundant processing to reset during program runaway. valid/invalid
7220 group user? manual 5-18 fig. 5.3.5 e 2 prom map when using rom correction function (2) e 2 prom address 023 16 contents instructions in correction program stored data (machine instruction) rom correction function 2 (55h: valid, others: invalid) 55h 024 16 rom correction function 2 execution address (high-order) feh 025 16 rom correction function 2 execution address (low-order) 96h 026 16 rom correction function 2 25h correction code 1 027 16 rom correction function 2 9dh correction code 2 028 16 rom correction function 2 25h correction code 3 029 16 rom correction function 2 01h correction code 4 02a 16 rom correction function 2 3ah correction code 5 02b 16 rom correction function 2 cah correction code 6 02c 16 rom correction function 2 10h dex correction code 7 02d 16 rom correction function 2 f7h bpl 02e0h correction code 8 02e 16 rom correction function 2 60h correction code 9 02f 16 rom correction function 2 eah correction code 10 030 16 rom correction function 2 eah rts correction code 11 031 16 rom correction function 2 eah correction code 12 032 16 rom correction function 2 correction code 13 033 16 rom correction function 2 eah nop (see note) correction code 14 034 16 rom correction function 2 eah nop correction code 15 035 16 rom correction function 2 eah nop correction code 16 036 16 rom correction function 2 eah nop correction code 17 037 16 rom correction function 2 eah nop correction code 18 038 16 rom correction function 2 eah nop correction code 19 039 16 rom correction function 2 eah nop correction code 20 03a 16 rom correction function 2 eah nop correction code 21 03b 16 rom correction function 2 eah nop correction code 22 03c 16 rom correction function 2 eah nop correction code 23 03d 16 rom correction function 2 eah nop correction code 24 03e 16 rom correction function 2 eah nop correction code 25 03f 16 rom correction function 2 eah nop correction code 26 040 16 rom correction function 2 eah nop correction code 27 041 16 rom correction function 2 eah nop correction code 28 042 16 rom correction function 2 eah nop correction code 29 043 16 rom correction function 2 4ch jmp yyxxh set reset vector address to yyxxh (see note). correction code 30 044 16 rom correction function 2 xxh correction code 31 045 16 rom correction function 2 yyh correction code 32 95h inc a lda 025h, x refer to ?igure 5.3.3 example a note: when operating normally, this instruction is not executed. this is a redundant processing to reset during program runaway. lda 0125h, x nop nop nop valid/invalid
7220 group user? manual 5-19 fig. 5.3.6 general flowchart when using rom correction function 5.3.4 general flowchart figure 5.3.6 shows the general flowchart when using rom correction function. e 2 prom addresses in the flowchart corresponds to e 2 prom map (refer to ?igures 5.3.4 and 5.3.5 ). start use rom correction function 1 ? no yes after reset release, read the data from e 2 prom ?rom correction function 1 (address 000 16 ) ?rom correction function 2 (address 023 16 ) ? 55 16 : valid, others: invalid ?rom correction address 1 (high-order) 16 ? 001 16 of e 2 prom ?rom correction address 1 (low-order) 16 ? 002 16 of e 2 prom address 02c0 16 to 02df 16 ? 003 16 to 022 16 of e 2 prom rom correction enable register (b0 at address 021b 16 ) ? ??(disabled) use rom correction function 2 ? no yes ?rom correction address 2 (high-order) 16 ? 024 16 of e 2 prom ?rom correction address 1 (low-order) 16 ? 025 16 of e 2 prom address 02e0 16 to 02ff 16 ? 026 16 to 045 16 of e 2 prom rom correction enable register (b1 at address 021b 16 ) ? ?? (enabled) rom correction enable register (b1 at address 021b 16 ) ? ?? (disabled) end store execution address into rom correction address 1. store correction codes of rom correction function 1 into rom correction memory 1 (block 1). enable block 1 enable bit. store execution address into rom correction address 2. store correction codes of rom correction function 2 into rom correction memory 2 (block 2). enable block 2 enable bit. disable block 2 enable bit. rom correction enable register (b0 at address 021b 16 ) ? ?? (enabled) disable block 1 enable bit. valid/invalid valid/invalid address 0218 address 0217 address 021a address 0219
7220 group user? manual 5-20 5.3.5 notes on use when using the rom correction function, note the following. l specify the first address (op code address) of each instruction as the rom correction address. l use the rts , rti or jmp instruction (total of 3 bytes) to return from the correction program to the main program. l do not set the same address to rom correction addresses 1 and 2 (addresses 0217 16 to 021a 16 ).
7220 group users manual 5.4 example of i 2 c-bus interface control (m37221mx-xxxsp/fp) the m37221mx-xxxsp/fp has multi-master i 2 c-bus interface. this interface, offering both arbitration lost detection and synchronous functions, is useful for the multi-master serial communications. this paragraph explains transmit/receive control example of e 2 prom (m6m80012p) adaptable to the i 2 c- bus interface. for details on the i 2 c-bus interface, refer to 2.8 multi-master i 2 c-bus interface. 5.4.1 specifications l e 2 prom required: m6m80012p l synchronous clock: internal clock l standard clock mode: 100 khz l number of transfer bits: 8 bits l data format: addressing format l pins required: scl1, sda1 l direction of data transfer: msb first 5.4.2 connection example fig. 5.4.1 connection example p1 1 /scl1 p1 3 /sda1 m37221mx-xxxsp m6m80012p scl sda scl sda scl sda : serial clock : serial data
7220 group users manual 5-22 5.4.3 e 2 prom functions (1) byte write bytes are written by sending the start condition, slave address a0 16 , sub-address (1 byte), data (1 byte), and the stop condition from the master. writing to the e 2 prom will be started after the master sends the stop condition, that is, in synchronization with a rising edge of the sda signal. this writing will be automatically terminated by the on-chip sequential controller. in this period, no acknowledge bits are generated. figure 5.4.2 shows the byte write timing. fig. 5.4.2 byte write timing bus operation of master side: sda signal s p slave address (w) sub-address (n) data (n) s t a r t a c k a c k s t o p bus operation of slave side: : start condition : stop condition : acknowledge bit : write bit (0) s p ack w w (2) random address read in this mode, the data of an arbitrary address is read. to set the first-read address, the master sends the start condition, slave address a0 16 , and sub-address (1 byte). upon receiving the acknowledge bit (ack) from the e 2 prom, the master sends the restart condition signal and slave address a1 16 again. after ack is generated from the e 2 prom, the data of the corresponding sub-address is read out. after the data is output, no acknowledge bits are generated, but the stop condition is sent by the master, completing this read operation. fig. 5.4.3 random address read timing s p data (n) s t a r t a c k s t o p a c k a c k s s t a r t bus operation of master side: sda signal bus operation of slave side: : start condition : stop condition : acknowledge bit : write bit (0) s p ack w slave address (w) sub-address (n) slave address (r) w r r : read bit (1) : restart condition : no acknowledge bit r rs nack a c k n a c k
7220 group users manual 5.4.4 general flowchart the processing routines which controls i 2 c-bus devices branch to the write processing routine and the read processing routine. the data output processing routine is used as the common processing routine. (1) write processing routine fig. 5.4.4 flowchart of write processing routine disable multi-master i 2 c-bus interface interrupt. transmit the start condition and slave address (w). transmit sub-address and data. note 1: refer to (3) data output processing routine. transmit the stop condition. note 2: be sure to set between s1 and s1 within 10 machine cycles. setting for outputting the start condition in data output processing routine. a? ? write start initialization s2 (address 00db 16 ) s1d (address 00da 16 ) iice (bit6 at address 00fe 16 ) s1 (address 00d9 16 ) end i s1 (address 00f8 16 ) s1 (address 00f8 16 ) i a slave address (w) a0 16 data output 11000101 2 01001000 2 0 00010000 2 1 11000000 2 11010000 2 0 a: s1: s2: s1d: iice: bb: accumulator i 2 c status register i 2 c clock control register i 2 c control register multi-master i 2 c interface interrupt enable bit bit 5 of i 2 c status register within 10 machine cycles s slave address (w) a0 16 a c k sub-address a c k data a c k p a ? ?
7220 group users manual 5-24 (2) read processing routine fig. 5.4.5 flowchart of read processing routine s slave address (w) a0 16 a c k sub-address a c k data a c k p a ? ? r s slave address (r) a1 16 ? ? read start s1 (address 00d9 16 ) ? 00100000 2 (a) ? slave address (r) a1 16 (a) ? slave address (w) a0 16 transmit the start condition, slave address (w) , and sub-address. immediately before the last receive byte? input start (set dummy data to generate clock.) end of reception of the last receive byte preparation for judging of timeout. store recive data to internal ram data output timeout ? (see note 2) end pin (bit 4 at address 00d9 16 ) 1 1? data output yes no yes no waiting receive end yes (end) no (not end) yes no set to receive mode set ack return mode. ? ?? a after data is received, no acknowledge bits are generated, but the stop condition is sent by the master, completing this read operation. set to non-ack return mode. initialization s2 (address 00db 16 ) s1d (address 00da 16 ) s1 (address 00d9 16 ) iice (bit6 at address 00fe 16 ) ? 11000101 2 ? 01001000 2 ? 0 ? 00010000 2 disable multi-master i 2 c-bus interface. setting for outputting the start condition in data output processing routine. trx (bit 6 at address 00d9 16 ) ack bit (bit 6 at address 00db 16 ) ? 0 ? 0 ack bit (bit 6 at address 00db 16 ) ? 1 s0 (address 00d7 16 ) ? ff 16 i s1 (address 00f8 16 ) s1 (address 00f8 16 ) i ? 1 ? 11000000 2 ? 11010000 2 ? 0 ? transmit the stop condition. note 1: be sure to set between s1 and s1 within 10 machine cycles. transmit the restart condtion and slave address (r). a c k note 2: the timeout count is performed by software with interrupts, such as timers. accordingly, if receive 2 2 c-bus access is stopped by timeout, the obtained data is incorrect data. a: s0: s1: s2: s1d: iice: bb: trx: ack bit: pin: rs: accumulator i 2 c data shift register i 2 c status register i 2 c clock control register i 2 c control register multi-master i 2 c interface interrupt enable bit bus busy flag communication mode specification bit ack bit i 2 c-bus interface interrupt request bit restart condition within 10 machine cycles operation does not complete within a certain time, i c-bus access is stopped by outputting stop operation is not completed due to various influences, the loop continues. therefore, if receive condition. if i
7220 group users manual (3) data output processing routine the data output processing routine is the common routine within the transmit/receive processing routine. fig. 5.4.6 flowchart of data output processing routine data output s0 (address 00d7 16 ) ? data to be output end s1 (address 00d9 16 ) ? 11110000 2 1-byte data transmit completes? store the number of output bytes to internal ram the first byte ? store the next data to a the last byte ? = 1 (no ack) no ack? output a. yes n end preparation for judging timeout. no error trx = 0 : al = 1 : = 0 (completion of 1-byte data transmit) = 1 (not yet) yes no an error occurs when data transmit does not end within a certain period. an error such as timeout occurs ? trx (bit 6 at address 00d9 16 ) 1 0 or al (bit 3 at address 00d9 16 ) 1 1 ? error pin (bit 4 at address 00d9 16 ) 1 1 ? stop judging of timeout. lrb (bit 0 at address 00d9 16 ) 1 1 ? = 0 (ack) a: s0: s1: trx: al: pin: lrb: accumulator i 2 c data shift register i 2 c status register communication mode specification bit arbitration lost detecting flag multi-master i 2 c interface interrupt enable bit last receive bit arbitration lost is detected (error)
7220 m3-xxxsp/fp) 7220 group users manual 5.5 example of i 2 c-bus control by software (m37220 m3-xxxsp/fp) althogh, the m37220 m3-xxxsp/fp has no multi-master i 2 c-bus interface, it can control single-master i 2 c- bus by software. most tv systems can be controlled in this way. this paragraph explains transmit/receive control example of a single-chip color tv signal processor (m52340sp) adaptable to the i 2 c-bus interface. 5.5.1 specifications l single-chip color tv signal processor required: m52340sp l number of transfer bits: 8 bits l data format: addressing format l pins required: p2 1 , p2 0 l direction of data transfer: msb first 5.5.2 connection example fig. 5.5.1 connection example p2 0 /s clk p2 1 /s out m37220 m3-xxxsp/fp m52340sp scl sda scl sda scl sda : serial clock : serial data
7220 m3-xxxsp/fp) 7220 group users manual 5-27 5.5.3 single-chip color tv signal processor function (1) status read status is read by sending the start condition, slave address bb 16 . after ack is generated from the m52340sp, the status data is read out. after the status data is output, any acknowledge bit is not generated, but the stop condition is sent by the master. then this read operation is completed. fig. 5.5.2 staus read timing s s t a r t bus operation of master side: sda signal bus operation of slave side: : start condition : stop condition : acknowledge bit : read bit (1) : no acknowledge bit s p ack r nack p data (n) s t o p a c k slave address (r) r a c k n (2) byte write bytes are written by sending the start condition, slave address ba 16 , sub-address (1 byte), data (1 byte), and the stop condition from the master. fig. 5.5.3 byte write timing bus operation of master side: sda signal s slave address (w) sub-address (n) data (n) s t a r t a c k a c k a c k s t o p bus operation of slave side: : start condition : stop condition : acknowledge bit : write bit (0) s p ack w w p
7220 m3-xxxsp/fp) 7220 group users manual 5.5.4 general flowchart (1) write processing routine the processing routine which controls i 2 c-bus devices branch to the write processing routine and the read processing routine. the start condition, the stop condition and the data output processing routine are used as the common processing routine. fig. 5.5.4 flowchart of write processing routine write start writedata ? slave address (w) ba 16 f_ack = 0? data output data output yes (ack) a ram: flag: writedata no ack counter write data counter f_ack s slave address (w) ba 16 a c k sub-address a c k data a c k p a ? ? write data counter no ack counter = 0 start condition writedata ? sub-address f_ack = 0? yes (ack) no (no ack) no (no ack) write data counter = 0? yes (end) no (not yet) no ack counter ? no ack counter + 1 end ? stop condition bus h data output ? writedata ? write data write data counter ? write data counter C 1 stop condition no ack counter 3 3? yes (give up) no (try 3 times) = 1 (number of write bytes)
7220 m3-xxxsp/fp) 7220 group users manual 5-29 (2) read processing routine fig. 5.5.5 flowchart of read processing routine writedata ? slave address (w) a0 16 f_ack = 0? data output data output yes (ack) a no ack counter = 0 start condition writedata ? sub-address f_ack = 0? yes (ack) no (no ack) no (no ack) read start ram: flag: writedata no ack counter read data counter f_ack s slave address (w) a0 16 a c k sub-address a c k data n a c k p a ? ? r s slave address (r) a1 16 ?? a c k to m52340sp ? (see note 2) no (to other devices (cf. e 2 prom)) yes (sub-address is not necessary at reading) end ? read data counter = 0? yes (end) no (not yet) return nack stop condition return ack read data counter ? read data counter C 1 data input ? ? no ack counter ? no ack counter + 1 stop condition no ack counter 3 3? yes (give up) no (try 3 times) data output ? start condition ? writedata ? slave address (r) a1 16 f_ack = 0? yes (ack) no (no ack) ? bus h notes 1: nack = no ack branches according to whether the device needs sub-address or not. (see note 1) 2:
7220 m3-xxxsp/fp) 7220 group users manual (3) data output processing routine the data output, the start condition, the stop condition, and the bus h processing routines are the common routines within the transmit/receive processing routine. data output bit 0 of port p2 direction register = output mode bit counter = 0 carry flag = 1? return yes ram: flag: writedata bit counter f_ack rotate writedata left with carry flag p2 0 (sda) = 1 no no bit counter 3 8? p2 0 (sda) = 0 p2 1 (scl) = 1 wait 6 m s p2 1 (scl) = 0 bit counter ? bit counter + 1 bit 0 of port p2 direction register = input mode wait 6 m s p2 1 (scl) = 1 wait 6 m s p2 0 (sda) = 1? yes no f_ack = 1 f_ack = 0 p2 1 (scl) = 0 yes fig. 5.5.6 flowchart of data output processing routine
7220 m3-xxxsp/fp) 7220 group users manual 5-31 (6) bus h processing routine fig. 5.5.9 flowchart of bus h processing routine (4) start condition processing routine start condition p2 0 (sda) = 1 bit 0 of port p2 direction register = output mode wait 6 m s p2 1 (scl) = 1 p2 0 (sda) = 0 wait 6 m s p2 1 (scl) = 0 return fig. 5.5.7 flowchart of start condition processing routine (5) stop condition processing routine fig. 5.5.8 flowchart of stop condition processing routine stop condition bit 0 of port p2 direction register = output mode p2 0 (sda) = 0 p2 1 (scl) = 1 wait 6 m s p2 0 (sda) = 1 return bus h bit 0 of port p2 direction register = output mode p2 1 (scl) = 1 wait 6 m s p2 0 (sda) = 1 return
7220 m3-xxxsp/fp) 7220 group users manual (7) data input processing routine fig. 5.5.10 flowchart of data input processing routine data intput bit 0 of port p2 direction register = input mode bit counter = 0 p2 0 (sda) = 1? return yes ram: readdata bit counter carry flag = 1 no no bit counter 3 8? carry flag = 0 rotate readdata with carry flag, to left p2 1 (scl) = 1 bit counter ? bit counter + 1 yes p2 1 (scl) = 1 wait 6 m s
7220 m3-xxxsp/fp) 7220 group users manual 5-33 (8) return ack processing routine fig. 5.5.11 flowchart of return ack processing routine (9) return nack processing routine fig. 5.5.12 flowchart of return nack processing routine return ack bit 0 of port p2 direction register = output mode p2 0 (sda) = 0 wait 6 m s p2 1 (scl) = 1 wait 6 m s p2 1 (scl) = 0 return return nack bit 0 of port p2 direction register = output mode p2 0 (sda) = 1 wait 6 m s p2 1 (scl) = 1 wait 6 m s p2 1 (scl) = 0 return
7220 m3-xxxsp/fp) 7220 group users manual 5.5.5 data setting according to key processing examples of the m52340sp settings, corresponding to each actual tv set key input, are described below. (1) power on/off key input when power supply is supplied to the m52340sp by this input, the data is set to all registers (at sub-addresses 00 16 to 13 16 ). (2) tuning and search-related keys (ch up/down key, ch direct selection key) input when tuning, the color system data (refer to table 5.5.10 ) is set according to the determination result of the color system by the status data register (refer to table 5.5.1 ). also, the corresponding data is set when the color system search-related keys are input. however, note that the above-mentioned setting is valid only when setting auto (bit 5 at sub- address 06 16 , write data) to 0. when setting to 1, the data is automatically set inside the m52340sp. when tuning, the data is set as shown in table 5.5.1. (3) volume up/down key input when the volume up/down key is input, the data is set as shown in table 5.5.2. (4) screen-size-related keys input when the screen-related keys are input on tvs with various screen sizes (wide aspect tv, etc.), the screen size data and position data is set as shown in table 5.5.3. also, the data of each frequency (50 hz or 60 hz) is occasionally held. (5) picture data control key and picture memory switching key input when changing picture data, the data is set to the corresponding write data register as shown in table 5.5.4. table 5.5.1 data setting at tuning and searching sub-address 02 16 06 16 bit d5 d4 d1 d0, d1 data trap dbf dfa dl time sub-address 03 16 bit d0 to d6 data audio att table 5.5.2 data setting at volume up/down key input table 5.5.3 data setting at screen-size-related keys input sub-address 09 16 bit d3 to d6 data h phase table 5.5.4 data setting at picture data control key and picture memory switching key input sub-address 04 16 05 16 07 16 08 16 0a 16 bit d0 to d5 d0 to d6 d0 to d6 d0 to d6 d0 to d6 data sharpness contrast tint color bright
7220 m3-xxxsp/fp) 7220 group users manual 5-35 (6) data setting when changing aft (auto fine tuning) state to change the state of auto fine tuning at presetting ch and ordinary tuning, the bit is set as shown in table 5.5.5. (7) data setting when changing audio mute state when the audio mute key is input, the bit is set as shown in table 5.5.6. if it is necessary to delete the sound while tuning with the tuning key input or presetting ch, the bit is set as shown in table 5.5.6. (8) data setting when changing video mute state when muting the video on screen while tuning with the tuning key input, the bit is set as shown in table 5.5.7. (9) data setting when adjusting white balance when adjusting the tv picture in the factory, set the data shown in table 5.5.8 to ready the service mode for adjusting the white color. table 5.5.5 data setting when changing aft state sub-address 04 16 bit d6 data defeat table 5.5.6 data setting when changing audio mute state sub-address 01 16 bit d6 data a mute table 5.5.7 data setting when changing video mute state sub-address 0b 16 bit d6 data mute table 5.5.8 data setting when adjusting white color balance sub-address 13 16 bit d3 data sersw
7220 m3-xxxsp/fp) 7220 group users manual fig. 5.5.13 flowchart of poweron processing 5.5.6 flowchart of data setting according to key processing figures 5.5.13 to 5.5.15 show the flowcharts of controlling the m52340sp when there are various event inputs to the actual tv system. (1) poweron processing by power key input power on wait for stabilizing time to supply power source. end ?et write data register of m52340sp ?o mute video and audio; mute (d6 at sub-address 0b 16 ) ? ?? a mute (d6 at sub-address 01 16 ) ? ?? related processings: ?sd when power on ?rite last data to e 2 prom , etc. wait for muting time to release mute of picture and sound: mute (d6 at sub-address 0b 16 ) ? ?? a mute (d6 at sub-address 01 16 ) ? ??
7220 m3-xxxsp/fp) 7220 group users manual 5-37 (2) ch up/down key input processing ch up/down end to mute video and audio: mute (d6 at sub-address 0b 16 ) ? ?? a mute (d6 at sub-address 01 16 ) ? ?? related processings: ?hanging ch ?sd when changing ch ?rite last data to e 2 prom , etc. wait for muting time to release mute of picture and sound; mute (d6 at sub-address 0b 16 ) ? ?? a mute (d6 at sub-address 01 16 ) ? ?? set the following (color system): ?.58 (d2 at sub-address 09 16 ) ?tsc (d1 at sub-address 02 16 ) ?ecam (d0 at sub-address 09 16 ) fig. 5.5.14 flowchart of ch up/down key input processing
7220 m3-xxxsp/fp) 7220 group user? manual (3) processing of ?icture memory switching key?input fig. 5.5.15 flowchart of ?icture memory switching key?input processing picture memory switching end related processings: ?ead out picture data from ram ?hanging picture data ?sd when switching picture memory ?rite last data to e 2 prom , etc. set the following according to each picture memory mode: ?harpness (d0 to d5 at sub-address 04 16 ) ?ontrast (d0 to d6 at sub-address 05 16 ) ?int (d0 to d6 at sub-address 07 16 ) ?olor (d0 to d6 at sub-address 08 16 ) ?right (d0 to d6 at sub-address 0a 16 )
7220 m3-xxxsp/fp) 7220 group user? manual 5-39 5.5.7 register map the m52340sp has 2 kinds of registers; the status data regis ter and the write data registers. (1) status data register the status data register indicates various signal state from the m52340sp side. the state is confirmed by regularly reading each bit. fig. 5.5.16 status data register b7 b6 b5 b4 b3 b2 b1 b0 status data register b name status data register 0 1 color system determination bit 2 (ntsc) 2 color system determination bit 1 (secam) color system determination bit 0 (condition) functions after reset rw 0 0 0 0 : under determination 1 : determination is completed b2 0 0 1 1 b1 0 1 0 1 image system pal secam ntsc secam r rw rw 3 3.58/4.43 determination bit (3.58) 4 aft signal detection bit 0 (aft0) 5 aft signal detection bit 1 (aft1) 6 synchronous presence determination bit (coincidence) 7 frequency determination bit (50/60) 0 0 0 0 : without synchronization 1 : it is synchronization 0 0 : 50 hz 1 : 60 hz 0 0 : 4.43 mhz 1 : 3.58 mhz rw rw rw rw rw freq. pin1 aft out d5: aft1 d4: aft0 -100khz f 0 +100khz 1 1 1 0 0 0 0 1
7220 m3-xxxsp/fp) 7220 group user? manual n bit 0: color system determination bit 0 (condition) this bit indicates whether the color system is being determined or not. figure 5.5.16 shows the state of determination, according to the bit, when auto (bit 5 at sub-address 06 16 , write data) is set to ?.?when auto (bit 5 at sub-address 06 16 , write data) is set to ?,?bit 0 is invalid as the color system is not determined automatically. n bit 1: color system determination bit 1 (secam) bit 2: color system determination bit 2 (ntsc) these bits determine the color system. n bit 3: 3.58/4.43 determination bit (3.58) this bit determines whether a color signal sub-carrier of the color system is 3.58 mhz or 4.43 mhz. n bit 4: aft signal detection bit 0 (aft0) bit 5: aft signal detection bit 1 (aft1) these bits detect the level of the auto fine tuning signal. n bit 6: synchronous presence determination bit (coincidence) this bit determines whether pin h.out output is synchronized with the video signal or not. n bit 7: field frequency determination bit (50/60) this bit determines whether the field frequency is 50 hz or 60 hz. according to the state of this bit, the display position or a vertical direction size of video can be changed.
7220 m3-xxxsp/fp) 7220 group users manual 5-41 (2) write data register fig. 5.5.17 map of write data register sub-address write data register 00 16 d7 d6 pos/neg d5 d4 d3 d2 d1 d0 01 16 02 16 03 16 04 16 05 16 06 16 07 16 08 16 09 16 0a 16 0b 16 0c 16 0d 16 0e 16 0f 16 10 16 13 16 a mute trap dbf dfa 4.5/6.0 mute auto f trap afcg hst sersw tv/ext 3.58 ntsc secam defeat delay adj vco adj audio att sharpness contrast tint color h phase bright drive r drive b cut off r cut off g cut off b dl time : no function 12 16 11 16
7220 m3-xxxsp/fp) 7220 group users manual n delay adj this adjusts the rf agc delay point. the output level of tuner decreases when the value increase, the output level increases when the value decreases. n pos/neg this switch sets the vif output signal to either the positive or the negative modulation signal. when 0, the negative modulation signal is selected; when 1, the positive modulation signal is selected. n vco adj this register changes the free running frequency of vif vco. the frequency increases when the value increases, the frequency decreases when the value decreases. n a mute this is the audio mute on/off. n 4.5/6.0 this bit must be set to 1 when the sound carrier frequency is 4.5 mhz. set 0 when the frequency is other values. n dfa, dl time in order to adjust the color signal and the luminance signal is delayed using the on-chip delay-line. the dl time register adjusts the delay approximately, and the dfa register performes the fine adjustments. when dfa is 1, actual delay time is +50 ns; when 0, it is +0 ns. for relationship between dfa and dl time, refer to table 5.5.9. n dbf the m52340sp has 2 trap; the second trap extends the bandwidth of the trap, described below. dbf is the on/off switch for the second trap. when 1, it is on; when 0, it is off. dbf is used in secam and other methods. n trap this is the trap on/off switch for taking out the luminance signal (y-signal) by y/c separation (y = y-signal, c = color signal) of the composite video signal. when 1, it is on; when 0, it is off. n audio att data is set (0 to 127) to change the volume. data 0 1 2 3 4 5 6 7 dl time1 0 0 0 0 1 1 1 1 actual delay time 170 ns 120 ns 330 ns 280 ns 410 ns 360 ns 490 ns 440 ns dl time0 0 0 1 1 0 0 1 1 dfa 0 1 0 1 0 1 0 1 table 5.5.9 relationship between dfa and dl time
7220 m3-xxxsp/fp) 7220 group users manual 5-43 n sharpness, contrast, tint, color, bright data is set to change the picture data. some tvs have a picture mode function (such as the movie mode, standard mode), the fixed data is set according to the mode. accordingly, it is necessary to change the picture data when changing the picture mode. n defeat this switch turns defeat off when aft is on, and vice versa. n tv/ext this selects either a tvs signal or an external devices signal. this bit should be set to 0 when tvs signal is selected and set to 1 when an external devices signal is selected. n auto this determines whether the automatic determination of the color system is used or not. when auto is 0, manual determination is set; when 1, determination is performed automatically. n 3.58/ntsc/secam when setting auto (bit 5 at sub-address 06 16 , write data) to 1, these bits are automatically set inside the m52340sp. when setting auto to 0, it is necessary to set the data shown in table 5.5.10, according to the color system. n h phase the pictures horizontal position is adjusted. data is given every 50 hz or 60 hz and the data is set when frequency changes. for wide tvs etc., data is given for each screen size mode, and the data is set when the screen size mode changes. n drive r, drive b data is used to adjust the output amplitude ratio of r, g and b signals. since g is the fixed data, its ratio is adjusted by r and b. n mute this is the video mute on/off switch. n cut off r, cut off g, cut off b data is used to adjust the output dc level of r, g and b signals. n f trap this register performes the fine adjustments to the trap frequency of trap for y/c separation. color system pal secam ntsc3.58 ntsc4.43 d1 ntsc 0 0 1 1 d0 secam 0 1 0 0 table 5.5.10 setting of color system (at sub-address 09 16 , write data) d2 3.58 0 0 1 0
7220 m3-xxxsp/fp) 7220 group users manual n sersw this switch is for white balance adjustments of the tv picture in the factory. when sersw is 0, it is off; when 1, it is on. n hst this switch stops horizontal oscillation. when hst is 0, the oscillation continues; when 1, it stops. n afcg this switch increases afc gain. when afcg is 0, afc gain is normal; when 1, it is high.
7220 group users manual 5.6 application circuit example 5.6.1 application circuit example 1 fig. 5.6.1 application circuit example 1 (i 2 c-bus chassis) osc1 osc2 d-a int1 pwm0 pwm1 pwm2 sda1 scl1 x out x in v cc v sync h sync out r g b m37221mx-xxxsp/fp cnv ss v ss scl sda e 2 prom m6m80012p/22p mute power on/off v sync h sync vhf-l vhf-h uhf catv reset tv/video exchange sound multiplex exchange balance control treble control bass control low pass filter low pass filter electric tuner antenna pre-amplifier m34238mk-xxxgp remote controller scl sda teletext on timer led out r g b single-chip color tv signal processor (including volume, color, brightness, contrast and tint control. also including afc and synchronous information.) scl sda m52340sp reset p2 5 p2 0 p0 5 p0 6 p0 3 p0 4 p2 6 p2 1 p2 2 p2 3 p2 4 i 2 c bus sound multiplex input p3 0 p3 1 i 2 c-bus chassis (voltage synthesizer) 5v a-d key a-d2 a-d1 vol () vol (+) ch () ch (+) tv/ av pow note: the oscillation for osd can be also obtained from main clock (refer to application example 2). application 5.6 application circuit example 5-45
7220 group users manual fig. 5.6.1 application circuit example 2 (non-bus chassis) 5.6.2 application circuit example 2 d-a int1 a-d4 pwm0 pwm1 pwm2 pwm3 tim2 p2 3 p2 0 p3 3 p2 2 x out x in v cc v sync h sync out r g b m37220 m3-xxxsp/fp cnv ss v ss cs clk data in data out e 2 prom m6m80011p/21p pal secam mute power on/off v sync h sync vhf-l vhf-h uhf catv a-d key reset tv/video exchange sound multiplex exchange sharpness control tint control contrast control brightness control color control volume control low pass filter low pass filter band decoder electric tuner antenna synchronous input afc input pre-amplifier m34236mj-xxxgp remote controller out r g b a-d2 p2 7 p2 5 p2 6 p3 0 p3 1 pwm4 pwm5 p1 0 p1 1 ntsc4.43 ntsc3.58 p1 3 p1 4 a-d1 vol () vol (+) ch () ch (+) p2 1 p1 7 p3 2 p1 2 aft defeat tv/ av pow reset note: the oscillation for osd can be obtained from main clock, so external oscillation circuit can be omitted. non-bus chassis (voltage synthesizer) 5-46 application 5.6 application circuit example
7220 group user? manual 6-2 6.1 package outline
7220 group user?s manual appendix 6.2 termination of unused pins 6-3 p0 0 /pwm0Cp0 5 /pwm5 p0 6 /int2/a-d4 p0 7 /int1 p1 0 /out2 p1 1 /scl1 p1 2 /scl2 p1 3 /sda1 p1 4 /sda2 p1 5 /a-d1/int3 p1 6 /a-d2 p1 7 /a-d3 p2 0 /s clk p2 1 /s out p2 2 /s in p2 3 /tim3 p2 4 /tim2 p2 5 Cp2 7 p3 0 /a-d5 p3 1 /a-d6 p3 2 p3 3 /osc1 p3 4 /osc2 h sync v sync p5 2 /r p5 3 /g p5 4 /b p5 5 /out1 x out d-a 6.2 t ermination of un used pins table 6.2.1 termination of unused pins termination ] it is the same as m37221mx-xxxsp/fp. m37221mx-xxxsp/fp m37220 m3-xxxsp/fp pin ] p1 0 p1 1 p1 2 p1 3 p1 4 p3 0 /a-d5/da1 p3 0 /a-d6/da2 ] ] p5 5 /out ] ] ] input/ output input output i/o set the port direction registers for the input mode and pull-down through a resistor. open pull-down through a resistor.
7220 group users manual 6-4 6.3 notes on use notes on programming and equipping when using m37221m6-xxxsp/fp are described below. 6.3.1 notes on processor status register (1) initialization of processor status register the contents of processor status register (ps) are undefined except the i flag (i = 1) immediately after reset. therefore initialize the flags that affect execution of a program. especially be sure to initialize the t and d flags because they have an important effect on calculations. (2) how to refer to processor status register when referring to the processor status register (ps) contents, execute the php instruction to push the processor status register contents into the stack (s) + 1. and then read the contents of stack (s) + 1. if necessary, execute the plp instruction to pull the pushed ps contents. in that case, be sure to execute the nop instruction immediately after the plp instruction. main program initialization of flags reset fig. 6.3.1 initialization of flags in ps pushed ps (s) (s) + 1 fig. 6.3.2 stack contents after php instruction execution fig. 6.3.3 note when executing plp instruction execute nop instruction execute plp instruction
7220 group users manual appendix 6.3 notes on use 6-5 6.3.2 notes on decimal operation (1) how to execute arithmetic operation instructions in decimal operation mode to calculate in decimal notation, set the decimal operation mode flag (d) to 1 by using the sed instruction, and execute the adc and sbc instructions. after that, execute at least one instruction to execute the sec , clc, or cld instruction. (2) status flags in decimal operation mode when the adc or sbc instruction are executed in decimal operation mode (d flag = 1), the n, v, and z flags are invalid. the carry flag (c) is set to 1 when a carry occurs as a result of an arithmetic operation, or is cleared to 0 when a borrow occurs. therefore, the carry flag can be used to determine whether a carry or a borrow has occurred or not. be sure to initialize the c flag before each arithmetic operation. 6.3.3 notes on interrupts (1) executing bbc or bbs instruction when executing the bbc or bbs instruction to an interrupt request bit immediately after this bit is set to 0 by using a data transfer instruction ] 1 , execute one or more instructions before executing the bbc or bbs instruction. reason if the bbc or bbs instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to 0, the value of the interrupt request bit before being cleared to 0 is read. ] 1: data transfer instructions: ldm , lda , sta , stx , and sty instructions clear the interrupt request (request distinguish) bit to ??(no interrupt issued) nop (one or more instructions) execute bbc or bbs instruction fig. 6.3.5 execution of bbc or bbs instruction fig. 6.3.4 note in decimal arithmetic operation set the decimal mode flag d to ? execute adc or sbc instruction execute nop instruction execute sec , clc , or cld instruction
7220 group users manual 6-6 (2) how to switch an external interrupt detection edge for the products able to switch the external interrupt detection edge, switch it as figure 6.3.6. reason the interrupt circuit recognizes the switching of the detection edge as the change of external input signals. this may cause an unnecessary interrupt. 6.3.4 notes on serial i/o (1) initialization for the serial i/o for the serial i/o interrupt, initialize as figure 6.3.7. (2) write transmit data to transmit buffer when an external clock is used as the synchronous clock for the clock synchronous serial i/o, write the transmit data to the serial i/o shift register at high of the transfer clock input level. fig. 6.3.6 sequence for switching an external interrupt detection edge clear an interrupt enable bit to ??(interrupt disabled) switch the detection edge clear an interrupt request bit to ?? (no interrupt request issued) set the interrupt request bit to ??(interrupt enabled) fig. 6.3.7 initialization for serial i/o nop (one or more instructions) clear the serial i/o interrupt enable bit to ?? (interrupt disabled) clear the serial i/o interrupt request bit to ?? (no interrupt request issued) set the serial i/o interrupt enable bit to ?? (interrupt enabled) select the serial i/o mode (set the serial i/o port selection bit to ??
7220 group users manual appendix 6.3 notes on use 6-7 21 0 ff 1 0 ff 1 0 ff 1 1 0ff1 0 ff1 0ff1 1 0 ff 0 0ff0ff b acd timer 1 count source timer 1 value read timer 2 value timer 2 value read timer 2 interrupt request writing to timer 1 writing to timer 2 timer 1 interrupt request timer 2 count source timer 1 value 6.3.5 notes on timer when a timer value is read, the timer value at read timing + 1 may be read. reason figure 6.3.8 shows the relation between timer values and their values read. timer values are changed at the rising edge of the count source, but the values read are counted down at the falling edge of the count source. therefore, the timer value + 1 may be read in some read timings. figure 6.3.9 shows the relation between timer values and their values read when two 8-bit timers are connected in series. in this example, timers 1 and 2 are connected in series and an overflow signal of timer 1 is used as the count source of timer 2. the timer 2 values read are counted down at the falling edge of the count source. when timers 1 and 2 are used as a single 16-bit counter, the timer 2 values read take the same value at timing a and b (or at timing c and d) as shown in figure 6.3.9. this is because the count source of timer 2 changes at the falling edge of the count source of timer 1. interrupt request timer count source timer value timer value read writing to timer 1 21 0 ff 1 0 ff 1 1 0ff1 0ff1 0 fig. 6.3.8 relation between timer values and their values read (timer setting value = 2) fig. 6.3.9 relation between timer values and their values read when two timers are connected in series (timers 1 and 2 are connected, timer 1 setting value = 2, timer 2 setting value = 1)
7220 group users manual 6-8 6.3.6 notes on a-d comparator (1) signal source impedance for analog input make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 f to 1 f. further, be sure to verify the operation of application products on the user side. reason an analog input pin includes the capacitor for analog voltage comparison. accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. this may cause the a-d comparison precision to be worse. (2) note during an a-d conversion the comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. thus, make sure the following during an a-d comparison. l f(x in ) is 500 khz or more l do not execute the stp instruction and wit instruction 6.3.7 note on reset pin in case where the reset signal rise time is long, connect a ceramic capacitor or others across the reset pin and the v ss pin. and use a 1000 pf or more capacitor for high frequency use. when connecting the capacitor, note the following : l make the length of the wiring which is connected to a capacitor as short as possible. l be sure to check the operation of application products on the user side. reason ______ if the several nanosecond or several ten nanosecond impulse noise enters the reset pin, it may cause a microcomputer failure.
7220 group users manual appendix 6.3 notes on use 6-9 6.3.8 notes on input and output pins (1) fix of a port input level in stand-by state in stand-by state ] 2 for low-power dissipation, do not make input levels of an input port and an i/o port undefined, especially for i/o ports of the p-channel and the n-channel open-drain. pull-up (connect the port to v cc ) or pull-down (connect the port to v ss ) these ports through a resistor. when determining a resistance value, note the following points: l external circuit l variation of output levels during the ordinary operation when using built-in pull-up or pull-down resistor, note on varied current values. l when setting as an input port : fix its input level l when setting as an output port : prevent current from flowing out to external reason even when setting as an output port with its direction register, in the following state : l n-channel......when the content of the port latch is 1 the transistor becomes the off state, which causes the ports to be the high-impedance state. note that the level becomes undefined depending on external circuits. accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an i/o port are undefined. this may cause power source current. ] 2 stand-by state : the stop mode by executing the stp instruction the wait mode by executing the wit instruction (2) modify of the contents of i/o port latch when the port latch of an i/o port is modified with the bit managing instruction ] 3 , the value of the unspecified bit may be changed. reason the bit managing instructions ] 3 are read-modify-write form instructions for reading and writing data by a byte unit. accordingly, when these instructions are executed on a bit of the data register of an i/o port, the following is executed to all bits of the data register. l as for a bit which is set for an input port : the pin state is read in the cpu, and is written to this bit after bit managing. l as for a bit which is set for an output port : the bit value is read in the cpu, and is written to this bit after bit managing. note the following : l even when a port which is set as an output port is changed for an input port, its data register holds the output data. l as for a bit of which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its data register contents ] 3 bit managing instructions : seb, and clb instruction 6.3.9 note on jmp instruction when using the jmp instruction (the indirect addressing mode), do not specify the last address in a page as an indirect address. memory (addresses 0000 16 to ffff 16 ) is separated into pages (by each 256 address).
7220 group users manual 6-10 6.3.10 note on multi-master i 2 c-bus interface this function is used at f(x in ) = 8.0 mhz of oscillation frequency. 6.3.11 termination of unused pins (1) proper termination of unused pins n output ports : open n input ports : connect each pin to v cc or v ss through each resistor of 1 kw to 10 kw. ports that permit the selecting of a built-in pull-up or pull-down resistor can also use this resistor. as for pins whose potential affects to operation modes such as pins cnv ss , int or others, select the v cc pin or the v ss pin according to their operation mode. n i/o ports : ?set the i/o ports for the input mode and connect them to v cc or v ss through each resistor of 1 k w to 10 k w . set the i/o ports for the output mode and open them at l or h. ?when opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. thus, the potential at these pins is undefined and the power source current may increase in the input mode. with regard to an effects on the system, thoroughly perform system evaluation on the user side. ?since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability. (2) incorrect termination of unused pins n input ports and i/o ports : do not open in the input mode. reason ?the power supply current may increase depending on the first-stage circuit. ?an effect due to noise may be easily produced as compared with proper termination (1). shown on the above. n i/o ports : set for input mode and do not connect to v cc or v ss directly. reason if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and v cc (or v ss ). n i/o ports : set for the input mode and do not connect multiple ports in a lump to v cc or v ss through a resistor. reason if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. (3) at the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins.
7220 group users manual appendix 6.4 countermeasures against noise 6-11 6.4 countermeasures against noise countermeasures against noise are described below. the following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 6.4.1 shortest wiring length the wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer. the shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) wiring for reset input pin make the length of wiring which is connected to the reset input pin as short as possible. especially, connect a capacitor across the reset input pin and the v ss pin with the shortest possible wiring (within 20mm). reason the width of a pulse input into the reset pin is determined by the timing necessary conditions. if noise having a shorter pulse width than the standard is input to the reset input pin, the reset is released before the internal state of the microcomputer is completely initialized. this may cause a program runaway. (2) wiring for clock input/output pins l make the length of wiring which is connected to clock l i/o pins as short as possible. l make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an oscillator and the v ss pin of a microcomputer as short as possible. l separate the v ss pattern only for oscillation from other v ss patterns. reason if noise enters clock i/o pins, clock waveforms may be deformed. this may cause a program failure or program runaway. also, if a potential difference is caused by the noise between the v ss level of a microcomputer and the v ss level of an oscillator, the correct clock will not be input in the microcomputer. reset reset circuit noise v ss v ss reset circuit v ss reset v ss n.g. o.k. fig.6.4.1 wiring for reset input pin noise x in x out v ss x in x out v ss n.g. o.k. fig.6.4.2 wiring for clock i/o pin
7220 group users manual 6-12 (3) wiring to cnvss pin connect the cnv ss pin to the v ss pin with the shortest possible wiring. reason the processor mode of a microcomputer is influenced by a potential at the cnv ss pin. if a potential difference is caused by the noise between pins cnv ss and v ss , the processor mode may become unstable. this may cause a microcomputer malfunction or a program runaway. (4) wiring to v pp pin of one time prom version and eprom version when the v pp pin is also used as the cnv ss pin ] 1 connect an approximately 5 kw resistor to the v pp pin the shortest possible in series and also to the v ss pin. when not connecting the resistor, make the length of wiring between the v pp pin and the v ss pin the shortest possible (refer to countermeasure example 1 of figure 6.4.4 ) ] 1 when a microcomputer has the cnv ss pin, the v pp pin is also used as the cnv ss pin. note : even when a circuit which included an approximately 5 kw resistor is used in the mask rom version, the micro- computer operates correctly. reason the v pp pin of the one time prom and the eprom version is the power source input pin for the built-in prom. when programming in the built-in prom, the impedance of the v pp pin is low to allow the electric current for writing flow into the prom. because of this, noise can enter easily. if noise enters the v pp pin, abnormal instruction codes or data are read from the built-in prom, which may cause a program runaway. fig.6.4.3 wiring for cnv ss pin noise cnv ss v ss cnv ss v ss n.g. o.k. fig.6.4.4 wiring for v pp pin of one time prom and eprom version cnv ss /v pp v ss in the shortest distance approximately 5k w
7220 group users manual appendix 6.4 countermeasures against noise 6-13 6.4.2 connection of a bypass capacitor across v ss line and v cc line connect an approximately 0.1 f bypass capacitor across the v ss line and the v cc line as follows: l connect a bypass capacitor across the v ss pin and the v cc pin at equal length. l connect a bypass capacitor across the v ss pin and the v cc pin with the shortest possible wiring. l use lines with a larger diameter than other signal lines for v ss line and v cc line. 6.4.3 wiring to analog input pins l connect an approximately 100 w to 1 k w resistor to an analog signal line which is connected to an analog input pin in series. besides, connect the resistor to the microcomputer as close as possible. l connect an approximately 1000 pf capacitor across the v ss pin and the analog input pin. besides, connect the capacitor to the v ss pin as close as possible. also, connect the capacitor across the analog input pin and the v ss pin at equal length. reason signals which is input in an analog input pin (such as an a-d converter/comparator input pin) are usually output signals from sensor. the sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. this long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. if a capacitor between an analog input pin and the v ss pin is grounded at a position far away from the v ss pin, noise on the gnd line may enter a microcomputer through the capacitor. fig.6.4.5 bypass capacitor across v ss line and v cc line v ss v cc chip fig.6.4.6 analog signal line and resistor and capacitor analog input pin v ss noise thermistor microcomputer n.g. o.k. (note) note : the resistor is used for dividing resistance with a thermistor.
7220 group users manual 6-14 6.4.4 oscillator concerns take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) keeping an oscillator away from large current signal lines install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. reason in the system using a microcomputer, there are signal lines for controlling motors, leds, and thermal heads or others. when a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) installing an oscillator away from signal lines where potential levels change frequently install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. reason signal lines where potential levels change frequently (such as the cntr pin signal line) may affect other lines at signal rising edge or falling edge. if such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. (3) oscillator protection using v ss pattern as for a two-sided printed circuit board, print a v ss pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. connect the v ss pattern to the microcomputer v ss pin with the shortest possible wiring. besides, separate this v ss pattern from other v ss patterns. x in x out v ss m microcomputer mutual inductance large current gnd fig.6.4.7 wiring for large current signal line x in x out v ss cntr do not cross n.g. fig.6.4.8 wiring for signal line where potential levels charge frequently x in x out v ss an example of v ss patterns on the underside of a printed circuit board oscillator wiring pattern example separate the v ss line for oscillation from other v ss lines fig.6.4.9 v ss pattern on underside of an oscillator
7220 group users manual appendix 6.4 countermeasures against noise 6-15 6.4.5 setup for i/o ports setup i/o ports using hardware and software as follows: l connect a resistor of 100 w or more to an i/o port in series. l as for an input port, read data several times by a program for checking whether input levels are equal or not. l as for an output port, since the output data may reverse because of noise, rewrite data to its data register at fixed periods. l rewrite data to direction registers and pull-up control registers (only the product having it) at fixed periods. when a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be output from this port. if this is undesirable, connect a capacitor to this port to remove the noise pulse. fig. 6.4.10 setup for i/o ports x in x out v ss x in x out v ss n.g. o.k.
7220 group users manual 6-16 6.4.6 providing of watchdog timer function by software if a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. this is equal to or more effective than program runaway detection by a hardware watchdog timer. the following shows an example of a watchdog timer provided by software. in the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. this example assumes that interrupt processing is repeated multiple times in a single main routine processing. l assigns a single byte of ram to a software watchdog timer (swdt) and writes the initial value n in the swdt once at each execution of the main routine. the initial value n should satisfy the following condition: n+1 (counts of interrupt processing executed in each main routine) as the main routine execution cycle may change because of an interrupt processing or others, the initial value n should have a margin. l watches the operation of the interrupt processing routine by comparing the swdt contents with counts of interrupt processing after the initial value n has been set. l detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: if the swdt contents do not change after interrupt processing. l decrements the swdt contents by 1 at each interrupt processing. l determins that the main routine operates normally when the swdt contents are reset to the initial value n at almost fixed cycles (at the fixed interrupt processing count). l detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: if the swdt contents are not initialized to the initial value n but continued to decrement and if they reach 0 or less. fig. 6.4.11 watchidog timer by software main routine (swdt) ? n cli main processing (swdt) interrupt processing routine errors n interrupt processing routine (swdt) ? (swdt)1 interrupt processing (swdt) main routine errors > 0 0 rti return =n? 0? 1 n
7220 group users manual appendix 6.5 memory assignment 6-17 sfr area special function register (refer to figures 2. 3. 3 and 2. 3. 4) not used not used interrupt vector area zero page special page internal ram ram for display internal rom internal ram decimal notation 0 255 383 1719 40960 65535 65502 65280 1536 192 49152 0000 16 00c0 16 00ff 16 017f 16 06b7 16 a000 16 ffff 16 ff00 16 0600 16 rom (16 k bytes) for m37221m4 crt display ram (96 bytes) (see note) 01bf 16 ram (320 bytes) for m37221m4 c000 16 rom (24 k bytes) for m37221m6 ram (384 bytes) for m37221m6 447 not used 10000 16 11fff 16 1ffff 16 note: refer to table 2.11.4 contents of crt display ram. rom for display 65536 73727 131071 crt display rom (8 k bytes) hexadecimal notation 0100 16 6.5 memory assignment fig. 6.5.1 memory assignment of m37221m4-xxxsp and m37221m6-xxxsp/fp
7220 group users manual 6-18 fig. 6.5.2 memory assignment of m37221m8-xxxsp and m37221ma-xxxsp sfr area special function register (refer to figures 2. 3. 3 to 2. 3. 5) internal ram rom for display rom correction memory (ram) interrupt vector area not used 10000 16 11fff 16 1ffff 16 crt display rom (8 k bytes) not used 2 page register not used note: refer to table 2.11.4 contents of crt display ram. internal ram internal rom internal ram zero page special page hexadecimal notation decimal notation 65535 65502 65280 0 192 255 511 not used not used ram for display 1719 24576 1536 959 767 704 535 540 65536 73727 rom correction memory block 1: addresses 02c0 16 to 02df 16 block 2: addresses 02e0 16 to 02ff 16 768 131071 0000 16 00c0 16 00ff 16 01ff 16 ffff 16 ffde 16 ff00 16 rom (32 k bytes) for m37221m8 033f 16 0300 16 02ff 16 02c0 16 0217 16 021b 16 06b7 16 6000 16 0600 16 crt display ram (96 bytes) (see note) 03bf 16 ram (512 bytes) for m37221m8 8000 16 rom (40 k bytes) for m37221ma ram (640 bytes) for m37221ma 831 32768 0100 16
7220 group users manual appendix 6.5 memory assignment 6-19 fig. 6.5.3 memory assignment of m37220 m3-xxxsp/fp 0000 16 00c0 16 00ff 16 013f 16 06b3 16 d000 16 sfr area special function register (refer to figures 4.5.3 and 4.5.4) not used not used ffff 16 ffde 16 ff00 16 0600 16 interrupt vector area not used 10000 16 10fff 16 1ffff 16 zero page crt display rom (4 k bytes) special page rom (12 k bytes) crt display ram (80 bytes) (note) ram (256 bytes) note: refer to table 4.5.7 contents of crt display ram. internal ram (192 bytes) ram for display internal rom internal ram (64 bytes) rom for display hexadecimal notation decimal notation 0 255 319 1719 53248 65535 65502 65280 1536 192 65536 69631 131071
7220 group users manual 6-20 6.6 sfr assignment p30s p31s pw0 pw1 pw2 pw3 pw4 pw5 pw6 pw7 pn2 pn3 pn4 sm0 sm1 sm2 sm3 sm5 sm6 b7 b0 0 sad0 sad1 sad2 sad3 sad4 sad5 sad6 rbw lrb ad0 aas al pin bb trx mst bc0 bc1 bc2 es0 als 10 bit sad bsel0 bsel1 ccr0 ccr1 ccr2 ccr3 ccr4 fast mode ack bit ack n sfr area (addresses c0 16 to df 16 ) d0 16 d1 16 d2 16 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 c0 16 c1 16 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c9 16 cb 16 cc 16 cd 16 ce 16 cf 16 ca 16 address port p5 (p5) port p5 direction register (d5) port p3 output mode control register (p3s) da-h register (da-h) da-l register (da-l) pwm0 register (pwm0) port p1 (p1) port p1 direction register (d1) port p3 (p3) port p3 direction register (d3) port p2 (p2) port p2 direction register (d2) register port p0 (p0) port p0 direction register (d0) pwm1 register (pwm1) pwm2 register (pwm2) pwm3 register (pwm3) pwm4 register (pwm4) pwm output control register 1 (pw) pwm output control register 2 (pn) serial i/o mode register (sm) serial i/o register (sio) bit allocation i c data shift register (s0) 2 i c address register (s0d) 2 i c status register (s1) 2 i c control register (s1d) 2 i c clock control register (s2) 2 00 16 00 16 : fix this bit to 0 (do not write 1) : < bit allocation > function bit : no function bit : fix this bit to 1 (do not write 0) name : 1 0 d1 d2 d3 d4 d5 d6 d7 d0 0 0 fig. 6.6.1 sfr assignment (including internal state immediately after reset and access characteristics) (1) (m37221mx-xxxsp/fp)
7220 group users manual appendix 6.6 sfr assignment 6-21 b7 b0 access characteristics ro rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw : read enabled, write enabled rw ro : read enabled, write disabled : indeterminate immediately after reset : 0 immediately after reset 0 1 ? < state immediately after reset > : 1 immediately after reset ? 00 16 b7 b0 ? 00 16 ? 00 16 ? ? ? ? ? 0 0 0 ? ? 0 0 ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? ? ? ? ? 00 16 ? ? ? ? 00 16 00 16 00 16 0 0 00 0 1? 0 state immediately after reset 00 16 00 16 00 16 00 16 00 16 00 16 00 16
7220 group users manual 6-22 fig. 6.6.2 sfr assignment (including internal state immediately after reset and access characteristics) (2) (m37221mx-xxxsp/fp) b7 b0 hr0 hr1 hr2 hr3 hr4 hr5 cv10 cv11 cv12 cv13 cv14 cv15 cv16 cv20 cv21 cv22 cv23 cv24 cv25 cv26 cs10 cs11 cs20 cs21 md10 md20 co01 co02 co03 co05 co11 co12 co13 co15 co21 co22 co23 co25 co31 co32 co33 co35 cc0 cc1 cc2 vsyc r/g/b out1 op5 op6 op7 hsyc ck0 ck1 adm0 adm1 adm2 adm4 adc0 adc1 adc2 adc4 adc3 adc5 t34m0 t34m1 t34m2 t34m3 t34m4 t12m0 t12m1 t12m2 t12m3 t12m4 ck0 re5 re4 re3 cm2 tm1r tm2r tm3r tm4r crtr vscr it3r ck0 msr 1t1r 1t2r s1r tm1e tm2e tm3e tm4e crte vsce it3e 1t1e 1t2e s1e mse t34m5 co04 co14 co24 co34 co06 co16 co26 co36 co07 co17 co27 co37 cc7 out2 iicr iice f0 16 f1 16 f2 16 f3 16 f4 16 f5 16 f6 16 f7 16 f8 16 f9 16 fa 16 fb 16 fc 16 fd 16 fe 16 ff 16 e0 16 e1 16 e2 16 e3 16 e4 16 e5 16 e6 16 e7 16 e8 16 e9 16 eb 16 ec 16 ed 16 ee 16 ef 16 ea 16 address crt control register (cc) crt port control register (crtp) a-d control register 1 (ad1) a-d control register 2 (ad2) timer 1 (tm1) vertical position register 2 (cv2) color register 0 (co0) color register 1 (co1) character size register (cs) border selection register (md) register horizontal position register (hr) vertical position register 1 (cv1) timer 2 (tm2) timer 3 (tm3) timer 4 (tm4) timer 12 mode register (t12m) timer 34 mode register (t34m) pwm5 register (pwm5) interrupt input polarity register (re) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) color register 2 (co2) color register 3 (co3) crt clock selection register (ck) cpu mode register (cpum) bit allocation n sfr area (addresses e0 16 to ff 16 ) : fix this bit to 0 (do not write 1) : < bit allocation > function bit : no function bit : fix this bit to 1 (do not write 0) name : 1 0 00 00 0 0 0 0 00 16 11111 00 00 0 00 00
7220 group users manual appendix 6.6 sfr assignment 6-23 ? b7 b0 0 ?????? ? 0 ?????? ? ???? 0000 ?? 00000 0 ? 00 16 ? 00 000 0 0 ff 16 07 16 ff 16 07 16 ? ? ? 00 00 0? 0 1 ? 0 00 16 ? 11 1 00 state immediately after reset 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 b7 b0 access characteristics ro ck0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw : read enabled, write enabled rw ro : read enabled, write disabled : 0 immediately after reset 0 1 ? < state immediately after reset > : 1 immediately after reset : indeterminate immediately after reset
7220 group users manual 6-24 217 16 218 16 219 16 21a 16 21b 16 b7 b0 rcr1 rcr0 address register rom correction address 1 (high-order) bit allocation n 2 page register area (addresses 217 16 to 21b 16 ) rom correction address 1 (low-order) rom correction address 2 (high-order) rom correction address 2 (low-order) rom correction enable register (rcr) : fix this bit to 0 (do not write 1) : < bit allocation > function bit : no function bit : fix this bit to 1 (do not write 0) name : 1 0 adl20 00 adl21 adl22 adl23 adl24 adl25 adl26 adl27 adh20 adh21 adh22 adh23 adh24 adh25 adh26 adh27 adl10 adl11 adl12 adl13 adl14 adl15 adl16 adl17 adh10 adh11 adh12 adh13 adh14 adh15 adh16 adh17 note: only m37221m8-xxxsp and m37221ma-xxxsp have this area. fig. 6.6.3 memory map of 2 page register (including internal state immediately after reset and access characteristics) (3) (only m37221m8-xxxsp and m37221ma-xxxsp)
7220 group users manual appendix 6.6 sfr assignment 6-25 b7 b0 ? ? ? ? state immediately after reset : 0 immediately after reset : undefined immediately after reset 0 1 ? < state immediately after reset > : 1 immediately after reset 00 16 b7 b0 access characteristics rw rw rw rw : read enabled, write enabled rw ro : read enabled, write disabled rw
7220 group users manual 6-26 n sfr area (addresses c0 16 to df 16 ) d0 16 d1 16 d2 16 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 c0 16 c1 16 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c9 16 cb 16 cc 16 cd 16 ce 16 cf 16 ca 16 address port p5 (p5) port p5 direction register (d5) port p3 output mode control register (p3s) da-h register (da-h) da-l register (da-l) pwm0 register (pwm0) port p1 (p1) port p1 direction register (d1) port p3 (p3) port p3 direction register (d3) port p2 (p2) port p2 direction register (d2) register port p0 (p0) port p0 direction register (d0) pwm1 register (pwm1) pwm2 register (pwm2) pwm3 register (pwm3) pwm4 register (pwm4) pwm output control register 1 (pw) pwm output control register 2 (pn) serial i/o mode register (sm) serial i/o regsiter (sio) da1 conversion register (da1) da2 conversion register (da2) p30s p31s pw0 pw1 pw2 pw3 pw4 pw5 pw6 pw7 pn2 pn3 pn4 sm0 b7 b0 bit allocation da1s da2s da10 sm1 sm2 sm3 sm5 sm6 da11 da12 da13 da14 da15 da20 da21 da22 da23 da24 da25 0 0 0 : fix this bit to 0 (do not write 1) : < bit allocation > function bit : no function bit : fix this bit to 1 (do not write 0) name : 1 0 fig. 6.6.4 sfr assignment (including internal state immediately after reset and access characteristics) (4) (m37220 m3-xxxsp/fp)
7220 group users manual appendix 6.6 sfr assignment 6-27 access characteristics : read enabled, write enabled rw ro : read enabled, write disabled : 0 immediately after reset : undefined immediately after reset 0 1 ? < state immediately after reset > : 1 immediately after reset state immediately after reset ? 00 16 b7 b0 ? 00 16 ? 00 16 ? ? ? ? ? 0 0 0 ? ? 0 0 ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? ? ? ? ? 00 16 ? ? ? ? ? ? 0 0 ? ? ?? ? ? 0 0 ? ? ?? ? ? ? ? 00 16 00 16 00 16 00 16 00 16 b7 b0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
7220 group users manual 6-28 f0 16 f1 16 f2 16 f3 16 f4 16 f5 16 f6 16 f7 16 f8 16 f9 16 fa 16 fb 16 fc 16 fd 16 fe 16 ff 16 e0 16 e1 16 e2 16 e3 16 e4 16 e5 16 e6 16 e7 16 e8 16 e9 16 eb 16 ec 16 ed 16 ee 16 ef 16 ea 16 address crt control register (cc) crt port control register (crtp) a-d control register 1 (ad1) a-d control register 2 (ad2) timer 1 (tm1) vertical position register 2 (cv2) color register 0 (co0) color register 1 (co1) character size register (cs) border selection register (md) register horizontal position register (hr) vertical position register 1 (cv1) timer 2 (tm2) timer 3 (tm3) timer 4 (tm4) timer 12 mode register (t12m) timer 34 mode register (t34m) pwm5 register (pwm5) interrupt input polarity register (re) test register (test) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) color register 2 (co2) color register 3 (co3) crt clock selection register (ck) cpu mode register (cpum) b7 b0 bit allocation hr0 hr1 hr2 hr3 hr4 hr5 cv10 cv11 cv12 cv13 cv14 cv15 cv16 cv20 cv21 cv22 cv23 cv24 cv25 cv26 cs10 cs11 cs20 cs21 md10 md20 co01 co02 co03 co05 co11 co12 co13 co15 co21 co22 co23 co25 co31 co32 co33 co35 cc0 cc1 cc2 vsyc r/g/b out op5 op6 op7 hsyc ck0 ck1 adm0 adm1 adm2 adm4 adc0 adc1 adc2 adc4 adc3 adc5 t34m0 t34m1 t34m2 t34m3 t34m4 t12m0 t12m1 t12m2 t12m3 t12m4 ck0 re5 re4 re3 cm2 tm1r tm2r tm3r tm4r crtr vscr it3r ck0 msr 1t1r 1t2r s1r tm1e tm2e tm3e tm4e crte vsce it3e 1t1e 1t2e s1e mse t34m5 00 00 0 0 0 n sfr area (addresses e0 16 to ff 16 ) : fix this bit to 0 (do not write 1) : < bit allocation > function bit : no function bit : fix this bit to 1 (do not write 0) name : 1 0 0 00 00 16 11111 00 0 00 0 0 fig. 6.6.5 sfr assignment (including internal state immediately after reset and access characteristics) (5) (m37220 m3-xxxsp/fp)
7220 group users manual appendix 6.6 sfr assignment 6-29 b7 b0 access characteristics ro ck0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw : read enabled, write enabled rw ro : read enabled, write disabled : 0 immediately after reset : undefined immediately after reset 0 1 ? < state immediately after reset > : 1 immediately after reset state immediately after reset ? b7 b0 0 ?????? ? 0 ?????? ? ???? 0000 ?? 00000 0 ? 00 16 ? 00 000 0 0 ff 16 07 16 ff 16 07 16 ? ? ? 00 00 0? 0 1 1 0 00 16 1 11 1 00 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 rw rw rw rw rw rw rw rw
7220 group users manual 6-30 6.7 control registers fig. 6.7.1 port pi direction register b7 b6 b5 b4 b3 b2 b1 b0 port pi direction register (di) (i=0,1,2) [addresses 00c1 16, 00c3 16 , 00c5 16 ] b name functions after reset r w port pi direction register 0 0 : port pi 0 input mode 1 : port pi 0 output mode 0 1 0 : port pi 1 input mode 1 : port pi 1 output mode 0 2 0 : port pi 2 input mode 1 : port pi 2 output mode 0 3 0 : port pi 3 input mode 1 : port pi 3 output mode 0 4 0 : port pi 4 input mode 1 : port pi 4 output mode 0 5 0 : port pi 5 input mode 1 : port pi 5 output mode 0 6 0 : port pi 6 input mode 1 : port pi 6 output mode 0 7 0 : port pi 7 input mode 1 : port pi 7 output mode 0 port pi direction register rw rw rw rw rw rw rw rw fig. 6.7.2 port p3 direction register b7 b6 b5 b4 b3 b2 b1 b0 port p3 direction register (d3) [address 00c7 16 ] b name functions after reset rw port p3 direction register 0 0 : port p3 0 input mode 1 : port p3 0 output mode 0 1 0 : port p3 1 input mode 1 : port p3 1 output mode 0 2 0 : port p3 2 input mode 1 : port p3 2 output mode 0 0 port p3 direction register nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. rw rw rw r 3 to 7 addresses 00c1 16 , 00c3 16 , 00c5 16 address 00c7 16
7220 group users manual appendix 6.7 control registers 6-31 fig. 6.7.3 port p5 direction register fig. 6.7.4 port p3 output mode control register b7 b6 b5 b4 b3 b2 b1 b0 port p3 output mode control register (p3s) [address 00cd 16 ] b name functions after reset r w port p3 output mode control register 0 0 : cmos output 1 : n-channel open-drain output 0 1 0 0 4 to 7 0 p3 0 output structure selection bit (p30s) p3 1 output structure selection bit (p31s) nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 : cmos output 1 : n-channel open-drain output 2, 3 note: m37220 m3-xxxsp/fp 0 2 da1 output enable bit 0 : p3 0 input/output 1 : da1 output 0 3 da2 output enable bit 0 : p3 1 input/output 1 : da2 output fix thes bits to 0. 00 rw rw rw r (see note) rw rw address 00cd 16 b7 b6 b5 b4 b3 b2 b1 b0 port p5 direction register (d5) [address 00cb 16 ] b name functions after reset rw port p5 direction register 0, 1 0 : crt output (r) 1 : output port p5 2 0 2 to 5 0 : crt output (g) 1 : output port p5 3 0 0 : crt output (b) 1 : output port p5 4 0 0 port p5 direction register nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 6, 7 0 : crt output (out1) 1 : output port p5 5 0 0 r rw rw rw rw r address 00cb 16
7220 group users manual 6-32 fig. 6.7.5 pwm output control register 1 b7 b6 b5 b4 b3 b2 b1 b0 pwm output control register 1 (pw) [address 00d5 b after reset rw pwm output control register 1 0 1 2 3 4 0 name functions da, pwm count source selection bit (pw0) 0 : count source supply 1 : count source stop p0 0 /pwm0 output selection bit (pw2) 0: p0 0 output 1: pwm0 output p0 1 /pwm1 output selection bit (pw3) 0: p0 1 output 1: pwm1 output p0 2 /pwm2 output selection bit (pw4) 0: p0 2 output 1: pwm2 output 5 p0 3 /pwm3 output selection bit (pw5) 0: p0 3 output 1: pwm3 output 6 p0 4 /pwm4 output selection bit (pw6) 0: p0 4 output 1: pwm4 output da/pn4 output selection bit (pw1) 0 : da output 1 : pn4 output 7 p0 5 /pwm5 output selection bit (pw7) 0: p0 5 output 1: pwm5 output 0 0 0 0 0 0 0 16 ] rw rw rw rw rw rw rw rw address 00d5 16 fig. 6.7.6 pwm output control register 2 b7 b6 b5 b4 b3 b2 b1 b0 pwm output control register 2 (pn) [address 00d6 b after reset rw pwm output control register 2 0, 1 2 3 4 0 name functions da output polarity selection bit (pn3) 0 : positive polarity 1 : negative polarity pwm output polarity selection bit (pn4) nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. da general-purpose output bit (pn5) 0 : output low 1 : output high 5 to 7 0 0 0 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 : positive polarity 1 : negative polarity 16 ] r rw rw rw r address 00d6 16
7220 group users manual appendix 6.7 control registers 6-33 fig. 6.7.7 i 2 c data shift register fig. 6.7.8 i 2 c address register b7 b6 b5 b4 b3 b2 b1 b0 i c data shift register (s0) [address 00d7 16 ] b functions after reset rw i c data shift register 0 to 7 this is an 8-bit shift register to store receive data and write transmit data. indeterminate 2 2 note: 2 to write data into the i c data shift register after setting the mst bit to 0 (slave mode), keep an interval of 8 machine cycles or more. name d0 to d7 rw b7 b6 b5 b4 b3 b2 b1 b0 0 read/write bit (rbw) 1 to 7 slave address (sad0 to sad6) 0: read 1: write 0 0 the address data transmitted from the master is compared with the contents of these bits. i 2 c address register i 2 c address register (s0d) [address 00d8 16 ] b name functions after reset rw rw rw address 00d7 16 address 00d8 16
7220 group users manual 6-34 fig. 6.7.9 i 2 c status register b7 b6 b5 b4 b3 b2 b1 b0 i 2 c status register (s1) [address 00d9 16 ] i 2 c status register 0 3 4 5 6, 7 b7 b6 0 0 : slave recieve mode 0 1 : slave transmit mode 1 0 : master recieve mode 1 1 : master transmit mode 1 2 0 0 0 1 0 b name functions after reset rw communication mode specification bits (trx, mst) 0 : bus free 1 : bus busy bus busy flag (bb) 0 : interrupt request issued 1 : no interrupt request issued i 2 c-bus interface interrupt request bit (pin) 0 : not detected 1 : detected arbitration lost detecting flag (al) (see note) 0 : address mismatch 1 : address match slave address comparison flag (aas) (see note) 0 : no general call detected 1 : general call detected general call detecting flag (ad0) (see note) 0 : last bit = 0 1 : last bit = 1 last receive bit (lrb) (see note) note : these bits and flags can be read out, but cannnot be written. indeterminate r r r r rw rw 0 rw address 00d9 16
7220 group users manual appendix 6.7 control registers 6-35 b7 b6 b5 b4 b3 b2 b1 b0 0 to 2 bit counter (number of transmit/recieve bits) (bc0 to bc2) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 3 i 2 c-bus interface use enable bit (eso) 0 : disabled 1 : enabled 4 data format selection bit (als) 0 : addressing mode 1 : free data format 5 addressing format selection bit (10bit sad) 0 : 7-bit addressing format 1 : 10-bit addressing format 6, 7 connection control bits between i c-bus interface and ports (bsel0, bsel1) b7 b6 connection port 0 0 : none 0 1 : scl1, sda1 1 0 : scl2, sda2 1 1 : scl1, sda1 scl2, sda2 0 0 0 0 0 i 2 c control register (s1d : address 00da 16 ) i 2 c control register b name functions after reset rw note: when using ports p1 1 -p1 4 as i c-bus interface, the output structure changes automatically from cmos output to n-channel open-drain output. however, set the port direction register to 1 (output mode). 2 2 rw rw rw rw rw fig. 6.7.10 i 2 c control register address 00da 16
7220 group users manual 6-36 fig. 6.7.11 i 2 c clock contorol register b7 b6 b5 b4 b3 b2 b1 b0 i 2 c clock control register (s2 : address 00db 16 ) i 2 c clock control register 0 to 4 scl frequency control bits (ccr0 to ccr4) 7 5 6 scl mode specification bit (fast mode) 0 : standard clock mode 1 : high-speed clock mode 0 standard clock mode b name functions after reset rw 0 0 0 ack bit (ack bit) ack clock bit (ack) 0 : ack is returned. 1 : ack is not returned. 0 : no ack clock 1 : ack clock high speed clock mode setup disabled setup disabled 00 to 02 setup disabled 333 03 setup disabled 250 04 100 400 (see note) 05 83.3 166 06 500/ccr value 1000/ccr value ... 17.2 34.5 1d 16.6 33.3 1e 16.1 32.3 1f (at f = 4 mhz, unit : khz) note: at 4000khz in the high-speed clock mode, the duty is as below . 0 period : 1 period = 3 : 2 in the other cases, the duty is as below. 0 period : 1 period = 1 : 1 setup value of ccr4Cccr0 rw rw rw rw address 00db 16
7220 group users manual appendix 6.7 control registers 6-37 fig. 6.7.12 serial i/o mode register b7 b6 b5 b4 b3 b2 b1 b0 serial i/o mode register (sm) [address 00dc 16 ] b name functions after reset rw serial i/o mode register 0, 1 internal synchronous clock selection bits (sm0, sm1) b1 b0 0 0: f(x in )/4 0 1: f(x in )/16 1 0: f(x in )/32 1 1: f(x in )/64 2 synchronous clock selection bit (sm2) 3 serial i/o port selection bit (sm3) 4 5 transfer direction selection bit (sm5) 7 0 0 0: p2 0 , p2 1 functions as port 1: s clk , s out 0: external clock 1: internal clock 0: lsb first 1: msb first nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. 6 fix this bit to 0. 0 0 0 0 0 0 serial input pin selection bit (sm6) 0: input signal from s in pin 1: input signal from s out pin rw rw rw rw rw rw r address 00dc 16
7220 group users manual 6-38 fig. 6.7.13 da n conversion register (only m37220 m3-xxxsp/fp) b7 b6 b5 b4 b3 b2 b1 b0 da n conversion register (dan) (n = 1 and 2) [address 00de 16 , 00df 16 ] b after reset r w da n conversion register 0 to 5 6 indeterminate 0 name functions da conversion set bits (dan0Cdan5) b0 b1 b2 b3 b4 b5 fix this bit to 0. 1 000000 00000 0 0000 0 0 111 1 1 11111 1 111111 : 1/64vcc : 2/64vcc : 61/64vcc : 62/64vcc : 63/64vcc : 0/64vcc 7 0 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. rw r r 0 fig. 6.7.14 horizontal position register b7 b6 b5 b4 b3 b2 b1 b0 horizontal position register (hr) [address 00e0 16 ] b name functions after reset rw horizontal position register 0 to 5 6, 7 horizontal display start positions (hr0 to hr5) 64 steps (00 16 to 3f 16 ) 0 0 nothing is assigned. these bits are write disable bits. when thses bits are read out, the values are 0. rw r addresses 00de 16 , 00df 16 address 00e0 16
7220 group users manual appendix 6.7 control registers 6-39 fig. 6.7.15 vertical position register n b7 b6 b5 b4 b3 b2 b1 b0 vertical position register n (cv1,cv2) (n = 1 and 2) [addresses 00e1 16, 00e2 16 ] b name functions after reset r w vertical position register n 0 to 6 7 vertical display start positions 128 steps (00 16 to 7f 16 ) indeterminate 0 (cv1 : cv10 to cv16) nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. (cv2 : cv20 to cv26) rw r addresses 00e1 16 , 00e2 16 fig. 6.7.16 character size register b7 b6 b5 b4 b3 b2 b1 b0 character size register (cs) [address 00e4 16 ] b name functions after reset r w character size register 0, 1 character size of block 1 selection bits (cs10, cs11) 00 : minimum size 01 : medium size 10 : large size 11 : do not set. indeterminate 2,3 4 to 7 0 character size of block 2 selection bits (cs20,cs21) 00 : minimum size 01 : medium size 10 : large size 11 : do not set. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. indeterminate rw rw r address 00e4 16
7220 group users manual 6-40 fig. 6.7.17 border selection register b7 b6 b5 b4 b3 b2 b1 b0 border selection register (md) [address 00e5 16 ] b name functions after reset r w border selection register 0 block 1 out1 output border selection bit (md10) 0 : same output as character output 1 : border output indeterminate 1 2 block 1 out1 output border selection bit (md20) 0 : same output as character output 1 : border output 0 0 3 to 7 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. indeterminate rw r rw r 0 note : m37220 m3-xxxsp/fp (see note) rw (see note) block 1 out output border selection bit (md10) 0 : same output as character output 1 : border output indeterminate 2 rw block 2 out output border selection bit (md20) 0 : same output as character output 1 : border output indeterminate address 00e5 16
7220 group users manual appendix 6.7 control registers 6-41 fig. 6.7.18 color register n b7 b6 b5 b4 b3 b2 b1 b0 color register n (co0 to co3) (n = 0 to 3) [addresses 00e6 16 to 00e9 16 ] b name functions after reset r w color register n 0 0 1 b signal output selection bit (con1) 0 : no character is output 1 : character is output 0 2 g signal output selection bit (con2) 0 : no character is output 1 : character is output 0 3 r signal output selection bit (con3) 0 : no character is output 1 : character is output 0 4 b signal output (background) selection bit (con4) 0 : no background color is output 1 : background color is output 0 5 out1 signal output control bit (con5) 0 : character is output 1 : blank is output 0 6 g signal output (background) selection bit (con6) 0 : no background color is output 1 : background color is output 0 7 r signal output (background) selection bit (con7) 0 : no background color is output 1 : background color is output 0 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. (see note 1) (see notes 1, 2) (see note 2) notes 1: when bit 5 = 0 and bit 4 = 1, there is output same as a character or border output from the out1 pin. do not set bit 5 = 0 and bit 4 = 0. 2: when only bit 7 = 1 and bit 5 = 0, there is output from the out2 pin. r rw rw rw rw rw rw rw (see note 3) 3: m37220 m3-xxxsp/fp 4 0 5 out signal output control bit (con5) 0 : character is output 1 : blank is output 0 6, 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. r rw r addresses 00e6 16 to 00e9 16
7220 group users manual 6-42 fig. 6.7.19 crt control register b7 b6 b5 b4 b3 b2 b1 b0 crt control register (cc) [address 00ea 16 ] b name functions after reset r w crt control register 0 all-blocks display control bit (note 1) (cc0) 0 : all-blocks display off 1 : all-blocks display on 0 1 block 1 display control bit (cc1) 0 : block 1 display off 1 : block 1 display on 0 2 0 : block 2 display off 1 : block 2 display on 0 3 to 6 0 7p1 0 /out2 pin switch bit (cc7) 0 notes 1: display is controlled by logical product (and) between the all-blocks display control bit and each block control bit. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. block 2 display control bit (cc2) rw rw rw r rw 0 : p1 0 1 : out2 7 0 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. 2 : m37220 m3-xxxsp/fp (see note 2) r address 00ea 16
7220 group users manual appendix 6.7 control registers 6-43 b7 b6 b5 b4 b3 b2 b1 b0 crt port control register (crtp) [address 00ec 16 ] b name functions after reset r w crt port control register 0h sync input polarity switch bit (hsyc) 0 : positive polarity 1 : negative polarity 0 1 0 : positive polarity 1 : negative polarity 0 2 r, g, b output polarity switch bit (r/g/b) 0 : positive polarity 1 : negative polarity 0 3 out2 output polarity switch bit (out2) 0 : positive polarity 1 : negative polarity 0 5 r signal output switch bit (op5) 0 : r signal output 1 : mute signal output 0 6 g signal output switch bit (op6) 0 : g signal output 1 : mute signal output 0 7 b signal output switch bit (op7) 0 : b signal output 1 : mute signal output 0 v sync input polarity switch bit (vsyc) rw rw rw rw 4 out1 output polarity switch bit (out1) 0 : positive polarity 1 : negative polarity 0rw rw rw rw note : m37220 m3-xxxsp/fp (see note) 3 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. 0 r 4 out output polarity switch bit (out) 0 : positive polarity 1 : negative polarity 0rw fig. 6.7.20 crt port control register address 00ec 16
7220 group users manual 6-44 fig. 6.7.21 crt clock selection register address 00ed 16 b7 b6 b5 b4 b3 b2 b1 b0 crt clock selection register (ck) [address 00ed b name functions after reset r w crt clock selection register 0, 1 crt clock selection bits (ck0,ck1) 0 since the main clock is used as the clock for display, the oscillation frequency is limited. because of this, the character size in width (horizontal) direction is also limited. in this case, pins osc1 and osc2 are also used as input ports p3 3 and p3 4 respectively. the clock for display is supplied by connecting the following across the pins osc1 and osc2. ? a ceramic resonator only for crt display and a feedback resistor ? a quartz-crystal oscillator only for crt display and a feedback resistor (note) 2 to 7 0 0 0 0 0 0 0 b1 the clock for display is supplied by connecting rc or lc across the pins osc1 and osc2. functions 10 b0 crt oscillation frequency = f(x in ) crt oscillation frequency = f(x in )/1.5 note: it is necessary to connect other ceramic resonator or quartz-crystal oscillator across the pins x 0 0 1 1 1 1 fix these bits to 0. in and x out . 16 ] rw rw
7220 group users manual appendix 6.7 control registers 6-45 fig. 6.7.22 a-d control register 1 b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 1 (ad1) [address 00ee 16 ] b after reset rw a-d control register 1 0 to 2 analog input pin selection bits (adm0, adm1, adm2) name functions b2 b1 b0 0 0 0 : a - d1 0 0 1 : a-d2 0 1 0 : a-d3 0 1 1 : a-d4 1 0 0 : a-d5 1 0 1 : a-d6 1 1 0 : 1 1 1 : 4 storage bit of comparison result (adm4) 0: input voltage < reference voltage 1: input voltage > reference voltage 5 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 indeterminate 0 0 do not set. 3 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. rw rw r r address 00ee 16 fig. 6.7.23 a-d control register 2 b7 b6 b5 b4 b3 b2 b1 b0 a-d control register 2(ad2) [address 00ef 16 ] b after reset rw a-d control register 2 0 to 5 6, 7 0 0 name functions d-a converter set bits (adc0, adc1, adc2, adc3, adc4, adc5) b0 b1 b2 b3 b4 b5 nothing is assigned. these bits are write disable bits. when these bits are reed out, the values are 0. 1 000000 00000 0 0000 0 0 111 1 1 11111 1 111111 : 3/128vcc : 5/128vcc : 123/128vcc : 125/128vcc : 127/128vcc : 1/128vcc rw r address 00ef 16
7220 group users manual 6-46 fig. 6.7.24 timer 12 mode register address 00f4 16 b7 b6 b5 b4 b3 b2 b1 b0 timer 12 mode register (t12m) [address 00f4 16 ] b after reset w timer 12 mode register 0 1 2 3 4 5 0 name functions timer 1 count source selection bit (t12m0) 0: f(x in )/16 1: f(x in )/4096 timer 2 count source selection bit (t12m1) 0: internal clock 1: external clock from p2 4 /tim2 pin timer 1 count stop bit (t12m2) 0: count start 1: count stop timer 2 count stop bit (t12m3) 0: count start 1: count stop timer 2 internal count source selection bit (t12m4) 0: f(x in )/16 1: timer 1 overflow fix this bit to 0. r 0 0 0 0 0 0 6,7 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. w r w r w r w r w r w r r
7220 group users manual appendix 6.7 control registers 6-47 fig. 6.7.25 timer 34 mode register fig. 6.7.26 interrupt input polarity register b7 b6 b5 b4 b3 b2 b1 b0 timer 34 mode register (t34m) [address 00f5 16 ] b after reset rw timer 34 mode register 0 1 2 3 6,7 0 name functions timer 3 count source selection bit (t34m0) 0: f(x in )/16 1: external clock timer 4 internal count source selection bit (t34m1) 0: timer 3 overflow 1: f(x in )/16 timer 3 count stop bit (t34m2) 0: count start 1: count stop timer 4 count stop bit (t34m3) 0: count start 1: count stop nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 0 0 0 4 timer 4 count source selection bit (t34m4) 0: internal clock 1: f(x in )/2 0 5 timer 3 external count source selection bit (t34m5) 0: external clock from p2 3 /tim3 pin 1: external clock from h sync pin 0 rw rw rw rw rw rw r address 00f5 16 address 00f9 16 b7 b6 b5 b4 b3 b2 b1 b0 interrupt input polarity register(re) [address 00f9 16 ] b name functions after reset r w interrupt input polarity register 0 int1 polarity switch bit (re3) 1, 2 0 0 3 0 : positive polarity 1 : negative polarity 0 4 0 : positive polarity 1 : negative polarity 0 5 0 : positive polarity 1 : negative polarity 0 6 0 7 0 0 0 int2 polarity switch bit (re4) int3 polarity switch bit (re5) nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. fix these bits to 0. fix this bit to 0. nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. indeterminate r rw rw rw rw r rw
7220 group users manual 6-48 fig. 6.7.27 cpu mode register b7 b6 b5 b4 b3 b2 b1 b0 cpu mode register (cpum) (cm) [address 00fb 16 ] b after reset rw cpu mode register 0, 1 2 3 to 5 0 1 name functions fix these bits to 0. fix these bits to 1. 1 stack page selection bit (cm2) 1 0: 0 page 1: 1 page 10 0 6, 7 indeterminate note: this bit is set to 1 after reset release. 1 11 rw rw rw rw address 00fb 16 fig. 6.7.28 interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 1 (ireq1) [address 00fc b name functions after reset rw interrupt request register 1 0 0 : no interrupt request issued 1 : interrupt request issued timer 1 interrupt request bit (tm1r) 1 timer 2 interrupt request bit (tm2r) 2 timer 3 interrupt request bit (tm3r) 3 timer 4 interrupt request bit (tm4r) 4 crt interrupt request bit (crtr) 5v sync interrupt request bit (vscr) 6 multi-master i 2 c-bus interface interrupt request bit (iicr) 7 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] ] : 0 can be set by software, but 1 cannot be set. int3 interrupt request bit (it3r) 0 : no interrupt request issued 1 : interrupt request issued ] 16 ] r r r r r r r r note : m37220 m3-xxxsp/fp (see note) 6 0 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. r address 00fc 16 (note)
7220 group users manual appendix 6.7 control registers 6-49 fig. 6.7.30 interrupt control register 1 (see note) note : m37220 m3-xxxsp/fp 6 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. r b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 1 (icon1) [address 00fe 16 ] b name functions after reset rw interrupt control register 1 0 timer 1 interrupt enable bit (tm1e) 0 : interrupt disabled 1 : interrupt enabled 0 1 timer 2 interrupt enable bit (tm2e) 0 2 timer 3 interrupt enable bit (tm3e) 0 3 timer 4 interrupt enable bit (tm4e) 0 4 crt interrupt enable bit (crte) 0 5 v sync interrupt enable bit (vsce) 0 6 multi-master i 2 c-bus interface interrupt enable bit (iice) 0 0 0 7 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled int3 interrupt enable bit (it3e) 0 : interrupt disabled 1 : interrupt enabled rw rw rw rw rw rw rw rw b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 2 (ireq2) [address 00fd b name functions after reset rw interrupt request register 2 0 int1 interrupt request bit (itir) 0 : no interrupt request issued 1 : interrupt request issued 1 int2 interrupt request bit (it2r) 2 serial i/o interrupt request bit (s1r) 3 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. 4 f(x in )/4096 interrupt request bit (msr) 5, 6 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 7 fix this bit to 0. 0 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 ] : 0 can be set by software, but 1 cannot be set. 0 0 ] 0 0 ] 0 ] 0 ] 0 : no interrupt request issued 1 : interrupt request issued 16 ] r r r r r r rw fig. 6.7.29 interrupt request register 2 address 00fd 16 address 00fe 16
7220 group users manual 6-50 fig. 6.7.31 interrupt control register 2 address 00ff 16 fig. 6.7.32 rom correction enable register address 0212 16 b7 b6 b5 b4 b3 b2 b1 b0 rom correction enable register (rcr) [address 0212 16 ] b name functions after reset rw rom correction enable register 0 block 1 enable bit (rcr0) 0 : disabled 1 : enabled 1 block 2 enable bit (rcr1) 2, 3 4 to 7 0 : disabled 1 : enabled nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0 0 0 0 0 fix these bits to 0. 0 5 b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 2 (icon2) [address 00ff 16 ] b name functions after reset rw interrupt control register 2 0 int1 interrupt enable bit (it1e) 0 : interrupt disabled 1 : interrupt enabled 1 int2 interrupt enable bit (it2e) 2 serial i/o interrupt enable bit (s1e) 3 fix this bit to 0. 4 f(x in )/4096 interrupt enable bit (mse) 5 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled fix these bits to 0. 0 0 0 0 0 0 00 0 0 to 7 rw rw rw rw rw rw 5
7220 group users manual appendix 6.8 ports 6-51 6.8 ports fig. 6.8.1 i/o pin block diagram (1) p0 6 /int2/a-d4, p0 7 /int1 n-channel open-drain output data bus direction register port latch n-channel open-drain output p0 0 /pwm0Cp0 5 /pwm5, p3 2 data bus direction register port latch indicates a pin. l m37221m4-xxxsp, m37221m6-xxxsp/fp, m37221m8-xxxsp, m37221ma-xxxsp p1 0 /out2, p1 1 /scl1, p1 2 /scl2, p1 3 /sda1, p1 4 /sda2, p1 5 /a-d1/int3, p1 6 /a-d2, p1 7 /a-d3, p2 0 /s clk , p2 1 /s out , p2 2 /s in , p2 3 /tim3, p2 4 /tim2, p2 5 Cp2 7 , p3 0 /a-d5, p3 1 /a-d6 (see notes 1, 2) l m37220 m3-xxxsp/fp p1 0 Cp1 4 , p1 5 /a-d/int3, p1 6 /a-d2, p1 7 /a-d3, p2 0 /s clk , p2 1 /s out , p2 2 /s in , p2 3 /tim3, p2 4 /tim2, p2 5 Cp2 7 , p3 0 /a-d5/da1, p3 1 /a-d6/da2 (see note 2) cmos output notes 1 : data bus direction register port latch when ports p1 1 Cp1 4 are used as multi-master i c-bus interface pin and when ports p2 serial i/o output pins, their output structure is n-channel open-drain output. for the output structure of ports p3 (in the case of n-channel open-drain output, the block diagram is the same as below). 2 : 2 0 , p2 1 are used as 0 , p3 1 , either cmos output or n-channel open-drain output is selected
7220 group users manual 6-52 input p3 3 /osc1, p3 4 cmos output l m37221m4-xxxsp, m37221m6-xxxsp/fp, m37221m8-xxxsp, m37221ma-xxxsp d-a, p5 2 /r, p5 3 /g, p5 4 /b, p5 5 /out1 l m37220 m3-xxxsp/fp d-a, p5 2 /r, p5 3 /g, p5 4 /b, p5 5 /out internal circuit internal circuit schmidt input h sync , v sync h sync or v sync indicates a pin. fig. 6.8.2 i/o pin block diagram (2)
7220 group user? manual appendix 6.9 machine instruction table 6-53 6.9 machine instruction table machine instructions
7220 group user? manual 6-54
7220 group user? manual appendix 6.9 machine instruction table 6-55
7220 group user? manual 6-56
7220 group user? manual appendix 6.9 machine instruction table 6-57
7220 group user? manual 6-58
7220 group user? manual appendix 6.9 machine instruction table 6-59
7220 group user? manual 6-60
7220 group user? manual appendix 6.9 machine instruction table 6-61
7220 group user? manual 6-62
7220 group users manual appendix 6.10 instruction code table 6-63 6.10 instruction code table 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0123456789 abcdef 0 1 2 3 4 5 6 7 8 a b c d e f 9 hexadecimal notation ind,x brk ora ora ora ora ora ora ora ora bpl bmi rti bvc rts bvs bra bcc bcs bne beq set stp wit php clc plp sec pha cli pla sei dey tya tay clv iny cld inx sed txa txs tsx dex nop and and and and and and and and jsr clt jsr bbs bbs bbs bbs bbs bbs bbs bbs bbs bbs bbs bbs bbs bbs bbs bbs bbc bbc bbc bbc bbc bbc bbc bbc bbc bbc bbc bbc bbc bbc bbc bbc eor eor eor eor eor eor eor eor adc adc adc adc adc adc adc adc sta sta sta sta sta sta sta lda lda lda lda lda lda lda lda cmp cmp cmp cmp cmp cmp cmp cmp sbc sbc sbc sbc sbc sbc sbc sbc jsr ldy ldy ldy ldy ldy ldx ldx ldx ldx ldx cpy cpy cpy cpx cpx cpx rrf jmp tax jmp jmp bit com tst sty sty sty stx stx stx asl asl asl asl asl rol rol rol rol rol lsr lsr lsr lsr lsr ror ror ror ror ror dec dec dec dec inc inc inc inc dec inc seb clb seb clb seb clb seb clb seb clb seb clb seb clb seb clb seb clb seb clb seb clb seb clb seb clb seb clb seb clb seb clb bit ldm ind,x ind,x ind,x ind,x ind,x ind,x ind,x ind,x ind,y ind,y ind,y ind,y ind,y ind,y ind,y ind,y imm imm imm imm imm imm imm imm imm imm abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs zp,ind zp,ind sp 0,a 0,a 0,a 0,a 1,a 1,a 2,a 2,a 3,a 3,a 4,a 4,a 5,a 5,a 6,a 6,a 7,a 7,a 1,a 1,a 2,a 2,a 3,a 3,a 4,a 4,a 5,a 5,a 6,a 6,a 7,a 7,a 0,zp 0,zp 1,zp 1,zp 2,zp 2,zp 3,zp 3,zp 4,zp 4,zp 5,zp 5,zp 6,zp 6,zp 7,zp 7,zp zp zp zp zp zp zp zp zp zp zp zp zp zp zp zp zp zp zp zp zp zp zp zp zp imm 0,zp 0,zp 1,zp 1,zp 2,zp 2,zp 3,zp 3,zp 4,zp 4,zp 5,zp 5,zp 6,zp 6,zp 7,zp 7,zp zp,x zp,x zp,x zp,x zp,x zp,x zp,x zp,x zp,x zp,x zp,x zp,x zp,x zp,x zp,x zp,y zp,x zp,x abs abs abs abs abs abs a a a a a a abs,y abs,y abs,y abs,y abs,y abs,y abs,y abs,y abs,x abs,x abs,x abs,x abs,x abs,x abs,x abs,x abs,x abs,x abs,x abs,x abs,y abs,x abs,x ind zp abs,x d 3 Cd 0 d 7 Cd 4
7220 group user? manual 6-64 6.11 mask rom ordering method when placing an order, please submit the information described below. m37221m4-xxxsp mask rom ordering confirmation form.........1 set (please use the pages p6-65 to p6-67) m27221m8-xxxsp mask rom ordering confirmation form.........1 set (please use the pages p6-68 to p6-70) m37221m6-xxxsp/fp mask rom ordering confirmation form.........1 set (please use the pages p6-71 to p6-73) m27221ma-xxxsp mask rom ordering confirmation from.........1 set (please use the pages p6-74 to p6-76) m27220 m3-xxxsp/fp mask rom ordering confirmation from.........1 set (please use the pages p6-77 to p6-79) data to be written to mask rom.........eprom (dip type 27c101) (please provide 3 sets containing the identical data) a mark specification form.........1 set (please use the pages p6-80 and p6-81)
7220 group user? manual appendix 6.11 mask rom ordering method 6-65 gzz?h10?0b < 59b0 > 740 family mask rom confirmation form single-chip microcomputer m37221m4-xxxsp mitsubishi electric mask rom number date : supervisor signature receipt section head signature h customer company name date issued date : tel ( ) note : please fill in all items marked h . submitted by supervisor issuance signature h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) 27c101 eprom address 0000 16 product name ascii code : ?37221m4 000f 16 ffff 16 set ?f 16 ?in the shaded area. write the ascii codes that indicates the product name of ?37221m4 to addresses 0000 16 to 000f 16 . (1) (2) eprom type (indicate the type used) c000 16 character rom 1-a 107ff 16 117ff 16 h 2. mark specification mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (42p4b for m37221m4-xxxsp) and attach to the mask rom confirmation form. (1/3) do you set ?f 16 ?in the shaded area ? do you write the ascii codes that indicates the product name of ?37221m4 to addresses 0000 16 to 000f 16 ? eprom data check item (refer the eprom data and check 3 ?in the appropriate box) ? yes ? yes l l 10000 16 10fff 16 character rom 1-b data rom 16 k bytes 10800 16 character rom 2-a 11000 16 11800 16 character rom 1-b 11fff 16 1ffff 16 h 3. comments
7220 group user? manual 6-66 gzz?h10?0b <59b0 > 740 family mask rom confirmation form single-chip microcomputer m37221m4-xxxsp mitsubishi electric ? = 16 4d 16 ? = 33 16 ? = 3 7 16 ? = 3 2 16 ? = 32 16 ? = 3 1 16 ? = 4d 16 ? = 34 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 address = 16 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 address addresses 0000 16 to 000f 16 store the product name, and addresses 10000 16 to 11fff 16 store the character pattern. if the name of the product contained in the eproms does not match the name on the mask rom confirmation form, the rom processing is disabled. write the data correctly. inputting the name of the product with the ascii code ascii codes ?37221m4-?are listed on the right. the addresses and data are in hexadecimal notation. 1. inputting the character rom input the character rom data by dividing it into character rom1 and character rom2. for the character rom data, see the next page and on. 2. writing the product name and character rom data onto eproms (2/3)
7220 group user? manual appendix 6.11 mask rom ordering method 6-67 gzz?h10?0b< 59b0 > 740 family mask rom confirmation form single-chip microcomputer m37221m4-xxxsp mitsubishi electric the structure of character rom (divided of 12 5 16 dots font) example character code ?a 16 example 101a0 16 to 101af 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 00 16 04 16 04 16 0a 16 0a 16 11 16 11 16 11 16 20 16 20 16 3f 16 40 16 40 16 40 16 00 16 00 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f8 16 f8 16 f8 16 f4 16 f4 16 f4 16 f0 16 f0 16 example 109a0 16 to 109af 16 character rom1 character rom2 f 16 (3/3) (note) write the character code ?0 16 ?to ?f 16 ? to addreses 10000 16 to 10fff 16 . write the character code ?0 16 ?to ?f 16 ? to addreses 11000 16 to 11fff 16 .
7220 group user? manual 6-68 gzz?h11?8b < 72a0 > 740 family mask rom confirmation form single-chip microcomputer m37221m8-xxxsp mitsubishi electric mask rom number date : supervisor signature receipt section head signature h customer company name date issued date : tel ( ) note : please fill in all items marked h . submitted by supervisor issuance signature h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) 27c101 eprom address 0000 16 product name ascii code : ?37221m8 000f 16 ffff 16 set ?f 16 ?in the shaded area. write the ascii codes that indicates the product name of ?37221m8 to addresses 0000 16 to 000f 16 . (1) (2) eprom type (indicate the type used) 8000 16 character rom 1-a 107ff 16 117ff 16 h 2. mark specification mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (42p4b for m37221m8-xxxsp) and attach to the mask rom confirmation form. (1/3) do you set ?f 16 ?in the shaded area ? do you write the ascii codes that indicates the product name of ?37221m8 to addresses 0000 16 to 000f 16 ? eprom data check item (refer the eprom data and check 3 ?in the appropriate box) ? yes ? yes l l 10000 16 10fff 16 character rom 1-b data rom 32 k bytes 10800 16 character rom 2-a 11000 16 11800 16 character rom 1-b 11fff 16 1ffff 16 h 3. comments
7220 group user? manual appendix 6.11 mask rom ordering method 6-69 gzz?h11?8b <72a0 > 740 family mask rom confirmation form single-chip microcomputer m37221m8-xxxsp mitsubishi electric ? = 16 4d 16 ? = 33 16 ? = 3 7 16 ? = 3 2 16 ? = 32 16 ? = 3 1 16 ? = 4d 16 ? = 38 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 address = 16 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 address addresses 0000 16 to 000f 16 store the product name, and addresses 10000 16 to 11fff 16 store the character pattern. if the name of the product contained in the eproms does not match the name on the mask rom confirmation form, the rom processing is disabled. write the data correctly. inputting the name of the product with the ascii code ascii codes ?37221m8-?are listed on the right. the addresses and data are in hexadecimal notation. 1. inputting the character rom input the character rom data by dividing it into character rom1 and character rom2. for the character rom data, see the next page and on. 2. writing the product name and character rom data onto eproms (2/3)
7220 group user? manual 6-70 gzz?h11?8b< 72a0 > 740 family mask rom confirmation form single-chip microcomputer m37221m8-xxxsp mitsubishi electric the structure of character rom (divided of 12 5 16 dots font) example character code ?a 16 example 101a0 16 to 101af 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 00 16 04 16 04 16 0a 16 0a 16 11 16 11 16 11 16 20 16 20 16 3f 16 40 16 40 16 40 16 00 16 00 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f8 16 f8 16 f8 16 f4 16 f4 16 f4 16 f0 16 f0 16 example 109a0 16 to 109af 16 character rom1 character rom2 f 16 (3/3) (note) write the character code ?0 16 ?to ?f 16 ? to addreses 10000 16 to 10fff 16 . write the character code ?0 16 ?to ?f 16 ? to addreses 11000 16 to 11fff 16 .
7220 group user? manual appendix 6.11 mask rom ordering method 6-71 gzz?h09?6b < 52c0 > 740 family mask rom confirmation form single-chip microcomputer m37221m6-xxxsp/fp mitsubishi electric mask rom number date : supervisor signature receipt section head signature h customer company name date issued date : tel ( ) note : please fill in all items marked h . submitted by supervisor issuance signature h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) 27c101 eprom address 0000 16 product name ascii code : ?37221m6 000f 16 ffff 16 set ?f 16 ?in the shaded area. write the ascii codes that indicates the product name of ?37221m6 to addresses 0000 16 to 000f 16 . (1) (2) eprom type (indicate the type used) a000 16 character rom 1-a 107ff 16 117ff 16 h 2. mark specification mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (42p4b for m37221m6-xxxsp, 42p2r-a for m37221m6-xxxfp) and attach to the mask rom confirmation form. (1/3) do you set ?f 16 ?in the shaded area ? do you write the ascii codes that indicates the product name of ?37221m6 to addresses 0000 16 to 000f 16 ? eprom data check item (refer the eprom data and check 3 ?in the appropriate box) ? yes ? yes l l 10000 16 10fff 16 character rom 1-b data rom 24 k bytes 10800 16 character rom 2-a 11000 16 11800 16 character rom 1-b 11fff 16 1ffff 16 h 3. comments
7220 group user? manual 6-72 gzz?h09?6b <52c0 > 740 family mask rom confirmation form single-chip microcomputer m37221m6-xxxsp/fp mitsubishi electric ? = 16 4d 16 ? = 33 16 ? = 3 7 16 ? = 3 2 16 ? = 32 16 ? = 3 1 16 ? = 4d 16 ? = 36 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 address = 16 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 address addresses 0000 16 to 000f 16 store the product name, and addresses 10000 16 to 11fff 16 store the character pattern. if the name of the product contained in the eproms does not match the name on the mask rom confirmation form, the rom processing is disabled. write the data correctly. inputting the name of the product with the ascii code ascii codes ?37221m6-?are listed on the right. the addresses and data are in hexadecimal notation. 1. inputting the character rom input the character rom data by dividing it into character rom1 and character rom2. for the character rom data, see the next page and on. 2. writing the product name and character rom data onto eproms (2/3)
7220 group user? manual appendix 6.11 mask rom ordering method 6-73 gzz?h09?6b< 52c0 > 740 family mask rom confirmation form single-chip microcomputer m37221m6-xxxsp/fp mitsubishi electric the structure of character rom (divided of 12 5 16 dots font) example character code ?a 16 example 101a0 16 to 101af 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 00 16 04 16 04 16 0a 16 0a 16 11 16 11 16 11 16 20 16 20 16 3f 16 40 16 40 16 40 16 00 16 00 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f8 16 f8 16 f8 16 f4 16 f4 16 f4 16 f0 16 f0 16 example 109a0 16 to 109af 16 character rom1 character rom2 f 16 (3/3) (note) write the character code ?0 16 ?to ?f 16 ? to addreses 10000 16 to 10fff 16 . write the character code ?0 16 ?to ?f 16 ? to addreses 11000 16 to 11fff 16 .
7220 group user? manual 6-74 gzz?h10?6b < 5za0 > series melps 740 mask rom confirmation form single-chip microcomputer m37221ma-xxxsp mitsubishi electric mask rom number date : supervisor signature receipt section head signature h customer company name date issued date : tel ( ) note : please fill in all items marked h . supervisor issuance signature h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) 27c101 eprom address 0000 16 product name ascii code : ?37221ma 000f 16 ffff 16 set ?f 16 ?in the shaded area. write the ascii codes that indicates the product name of ?37221ma to addresses 0000 16 to 000f 16 . (1) (2) eprom type (indicate the type used) 6000 16 character rom 1-a 107ff 16 h 2. mark specification mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (42p4b for m37221ma-xxxsp) and attach to the mask rom confirmation form. (1/3) do you set ?f 16 ?in the shaded area ? do you write the ascii codes that indicates the product name of ?37221ma to addresses 0000 16 to 000f 16 ? eprom data check item (refer the eprom data and check 3 ?in the appropriate box) ? yes ? yes l l 10000 16 10fff 16 data rom 40 k bytes 10800 16 11000 16 1ffff 16 h 3. comments character rom 2-a 11fff 16 character rom 1-b character rom 2-b 117ff 16 11800 16 submitted by
7220 group user? manual appendix 6.11 mask rom ordering method 6-75 gzz?h10?6b <5za0 > series melps 740 mask rom confirmation form single-chip microcomputer m37221ma-xxxsp mitsubishi electric ? = 16 4d 16 ? = 33 16 ? = 37 16 ? = 32 16 ? = 32 16 ? = 31 16 ? = 4d 16 ? = 41 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 address = 16 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 address addresses 0000 16 to 000f 16 store the product name, and addresses 10000 16 to 11fff 16 store the character pattern. if the name of the product contained in the eproms does not match the name on the mask rom confirmation form, the rom processing is disabled. write the data correctly. inputting the name of the product with the ascii code ascii codes ?37221ma-?are listed on the right. the addresses and data are in hexadecimal notation. 1. inputting the character rom input the character rom data by dividing it into character rom1 and character rom2. for the character rom data, see the next page and on. 2. writing the product name and character rom data onto eproms (2/3)
7220 group user? manual 6-76 gzz?h10?6b< 5za0 > series melps 740 mask rom confirmation form single-chip microcomputer m37221ma-xxxsp mitsubishi electric the structure of character rom (divided of 12 5 16 dots font) example character code ?a 16 example 101a0 16 to 101af 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 0 1 1 1 2 2 3 4 4 4 0 0 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f8 16 f8 16 f8 16 f4 16 f4 16 f4 16 f0 16 f0 16 example 109a0 16 to 109af 16 character rom1 character rom2 f 16 (3/3) 0 16 4 16 a 16 1 16 04 16 a 16 1 16 1 16 0 16 0 16 f 16 0 16 0 16 0 16 0 16 0 16 (note) write the character code ?0 16 ?to ?f 16 to addresses 10000 16 to 10fff 16 . write the character code ?0 16 ?to ?f 16 to addresses 11000 16 to 11fff 16 .
7220 group user? manual appendix 6.11 mask rom ordering method 6-77 gzz?h09?2b < 56b0 > 740 family mask rom confirmation form single-chip microcomputer m37220 m3-xxxsp mitsubishi electric mask rom number date : supervisor signature receipt section head signature h customer company name date issued date : tel ( ) note : please fill in all items marked h . supervisor submitted by issuance signature h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) 27c101 eprom address 0000 16 product name ascii code : ?37220 m3 000f 16 ffff 16 set ?f 16 ?in the shaded area. write the ascii codes that indicates the product name of ?37220 m3 to addresses 0000 16 to 000f 16 . (1) (2) eprom type (indicate the type used) d000 16 character rom 1 107ff 16 h 2. mark specification mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (42p4b for m37220 m3-xxxsp) and attach to the mask rom confirmation form. (1/3) do you set ?f 16 ?in the shaded area ? do you write the ascii codes that indicates the product name of ?37220 m3 to addresses 0000 16 to 000f 16 ? eprom data check item (refer the eprom data and check 3 ?in the appropriate box) ? yes ? yes l l 10000 16 10fff 16 data rom 12 k bytes 10800 16 character rom 2 11000 16 1ffff 16 h 3. comments
7220 group user? manual 6-78 gzz?h09?2b <56b0 > 740 family mask rom confirmation form single-chip microcomputer m37220 m3-xxxsp mitsubishi electric ? = 16 4d 16 ? = 33 16 ? = 37 16 ? = 32 16 ? = 32 16 ? = 30 16 ? = 4d 16 ? = 33 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 address = 16 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 address addresses 0000 16 to 000f 16 store the product name, and addresses 10000 16 to 10fff 16 store the character pattern. if the name of the product contained in the eproms does not match the name on the mask rom confirmation form, the rom processing is disabled. write the data correctly. inputting the name of the product with the ascii code ascii codes ?37220 m3-?are listed on the right. the addresses and data are in hexadecimal notation. 1. inputting the character rom input the character rom data by dividing it into character rom1 and character rom2. for the character rom data, see the next page and on. 2. writing the product name and character rom data onto eproms (2/3)
7220 group user? manual appendix 6.11 mask rom ordering method 6-79 gzz?h09?2b< 56b0 > 740 family mask rom confirmation form single-chip microcomputer m37220 m3-xxxsp mitsubishi electric the structure of character rom (divided of 12 5 16 dots font) example character code ?a 16 example 101a0 16 to 101af 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 0 1 1 1 2 2 3 4 4 4 0 0 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f0 16 f8 16 f8 16 f8 16 f4 16 f4 16 f4 16 f0 16 f0 16 example 109a0 16 to 109af 16 character rom1 character rom2 f 16 (3/3) 0 16 4 16 a 16 1 16 04 16 a 16 1 16 1 16 0 16 0 16 f 16 0 16 0 16 0 16 0 16 0 16
7220 group user? manual 6-80 6.12 mark specification form 42p4b (42-pin shrink dip) mark specification form
7220 group user? manual appendix 6.12 mark specification form 6-81 42p2r-a (42-pin shrink sop) mark specification form
7220 group jul. first edition 1997 editioned by committee of editing of mitsubishi semiconductor users manual published by mitsubishi electric corp., semiconductor marketing division this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?1997 mitsubishi electric corporation
7220 group ? 1997 mitsubishi electric corporation. new publication, effective jul. 1997. specifications subject to change without notice.
7220 group user's manual (1/1) revision description 971130 9708
